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    Short link efficient interconnect circuitry
    51.
    发明授权
    Short link efficient interconnect circuitry 有权

    公开(公告)号：US10530614B2

    公开(公告)日：2020-01-07

    申请号：US16230974

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: G06N20/00 ,  H04L25/03

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

    Multiple indirection granularities for mass storage devices
    52.
    发明授权
    Multiple indirection granularities for mass storage devices 有权

    公开(公告)号：US10409500B2

    公开(公告)日：2019-09-10

    申请号：US15699930

    申请日：2017-09-08

    Applicant: Intel Corporation

    Inventor： Sanjeev N. Trika ,  Peng Li ,  Jawad B. Khan

    IPC: G06F3/06 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F12/1009

    Abstract: One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LBAs, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.

    Logical block address to physical block address (L2P) table compression
    53.
    发明授权
    Logical block address to physical block address (L2P) table compression 有权

    公开(公告)号：US10365844B2

    公开(公告)日：2019-07-30

    申请号：US15394453

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： Peng Li ,  Sanjeev N. Trika

    IPC: G06F12/02 ,  G06F3/06

    Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.

    Apparatus, system and method for increasing the capacity of a storage device available to store user data
    54.
    发明授权
    Apparatus, system and method for increasing the capacity of a storage device available to store user data 有权

    公开(公告)号：US10296224B2

    公开(公告)日：2019-05-21

    申请号：US15387600

    申请日：2016-12-21

    Applicant: INTEL CORPORATION

    Inventor： Peng Li ,  William K. Lui ,  Sanjeev N. Trika

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

    Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.

    INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY
    58.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY 有权

    公开(公告)号：US20240418951A1

    公开(公告)日：2024-12-19

    申请号：US18795148

    申请日：2024-08-05

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Joel Martinez ,  Jon Long

    IPC: G02B6/43 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H04B10/40

    Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

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