中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

307 records (took 0.023 seconds)

    TECHNOLOGIES FOR TRUSTED I/O WITH A CHANNEL IDENTIFIER FILTER AND PROCESSOR-BASED CRYPTOGRAPHIC ENGINE
    51.
    发明申请
    TECHNOLOGIES FOR TRUSTED I/O WITH A CHANNEL IDENTIFIER FILTER AND PROCESSOR-BASED CRYPTOGRAPHIC ENGINE 审中-公开

    公开(公告)号：US20170364707A1

    公开(公告)日：2017-12-21

    申请号：US15628008

    申请日：2017-06-20

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Gideon Gerzon ,  Baruch Chaikin ,  Siddhartha Chhabra ,  Pradeep M. Pappachan ,  Bin Xing

    IPC: G06F21/62 ,  G06F21/57 ,  G06F21/60 ,  G06F13/20 ,  G06F21/51

    Abstract: Technologies for trusted I/O include a computing device having a processor, a channel identifier filter, and an I/O controller. The I/O controller may generate an I/O transaction that includes a channel identifier and a memory address. The channel identifier filter verifies that the memory address of the I/O transaction is within a processor reserved memory region associated with the channel identifier. The processor reserved memory region is not accessible to software executed by the computing device. The processor encrypts I/O data at the memory address in response to invocation of a processor feature and copies the encrypted data to a memory buffer outside of the processor reserved memory region. The processor may securely clean the processor reserved memory region before encrypting and copying the data. The processor may wrap and unwrap programming information for the channel identifier filter. Other embodiments are described and claimed.

    BINDING A TRUSTED INPUT SESSION TO A TRUSTED OUTPUT SESSION
    54.
    发明申请
    BINDING A TRUSTED INPUT SESSION TO A TRUSTED OUTPUT SESSION 有权
    将有争议的输入会议绑定到受信任的输出会议

    公开(公告)号：US20160380985A1

    公开(公告)日：2016-12-29

    申请号：US14752379

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Reshma Lal ,  Ulhas S. Warrier

    IPC: H04L29/06

    CPC classification number: H04L63/061 ,  G06F21/74 ,  G06F21/82 ,  H04L63/062 ,  H04L63/0876 ,  H04L67/146 ,  H04L2463/062

    Abstract: According to an embodiment provided herein, there is provided a system that binds a trusted output session to a trusted input session. The system includes a processor to execute an enclave application in an architecturally protected memory. The system includes at least one logic unit forming a trusted entity to, responsive to a request to set up a trusted I/O session, generate a unique session identifier logically associated with the trusted I/O session and set a trusted I/O session indicator to a first state. The system includes at least one logic unit forming a cryptographic module to, responsive to the request to set up the trusted I/O session, receive an encrypted encryption key and the unique session identifier from the enclave application; verify the unique session identifier; and responsive a successful verification, decrypt and save the decrypted encryption key in an encryption key register.

    Abstract translation: 根据本文提供的实施例，提供了将可信输出会话绑定到可信输入会话的系统。 该系统包括处理器，用于在架构受保护的存储器中执行飞地应用。 系统包括形成可信实体的至少一个逻辑单元，以响应于建立可信I / O会话的请求，生成与可信I / O会话逻辑关联的唯一会话标识符，并设置可信任I / O会话 指标到第一个状态。 该系统包括形成加密模块的至少一个逻辑单元，以响应于建立可信I / O会话的请求，从飞地应用接收加密的加密密钥和唯一的会话标识符; 验证唯一会话标识符; 并响应成功的验证，解密并将解密的加密密钥保存在加密密钥寄存器中。

    Virtualizing a hardware monotonic counter
    56.
    发明授权
    Virtualizing a hardware monotonic counter 有权
    虚拟化硬件单调计数器

    公开(公告)号：US09465933B2

    公开(公告)日：2016-10-11

    申请号：US13690111

    申请日：2012-11-30

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Reshma Lal ,  Jason Martin ,  Daniel Nemiroff

    IPC: G06F21/00 ,  G06F21/50 ,  G06F21/54 ,  G06F21/71

    CPC classification number: G06F21/50 ,  G06F21/54 ,  G06F21/71

    Abstract: Embodiments of an invention for virtualizing a hardware monotonic counter are disclosed. In one embodiment, an apparatus includes a hardware monotonic counter, virtualization logic, a first non-volatile storage location, and a second non-volatile storage location. The virtualization logic is to create a virtual monotonic counter from the hardware monotonic counter. The first non-volatile storage location is to store an indicator that the count of the hardware monotonic counter has changed. The second non-volatile storage location is to store an indicator that the count of the virtual monotonic counter has changed.

    Abstract translation: 公开了用于虚拟化硬件单调计数器的发明的实施例。 在一个实施例中，装置包括硬件单调计数器，虚拟化逻辑，第一非易失性存储位置和第二非易失性存储位置。 虚拟化逻辑是从硬件单调计数器创建一个虚拟单调计数器。 第一个非易失性存储位置是存储硬件单调计数器的计数改变的指示符。 第二非易失性存储位置是存储虚拟单调计数器的计数改变的指示符。

    CACHE-LESS SPLIT TRACKER ARCHITECTURE FOR REPLAY PROTECTION TREES
    57.
    发明申请
    CACHE-LESS SPLIT TRACKER ARCHITECTURE FOR REPLAY PROTECTION TREES 有权
    高速缓存分离器跟踪器架构，用于替换保护条

    公开(公告)号：US20160283405A1

    公开(公告)日：2016-09-29

    申请号：US14671659

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Jungju Oh ,  Siddhartha Chhabra ,  David M. Durham

    IPC: G06F12/14 ,  G06F21/60

    CPC classification number: G06F12/1408 ,  G06F12/0875 ,  G06F21/602 ,  G06F2212/1052

    Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.

    Abstract translation: 系统，装置和方法可以提供接收访问由计数器模式加密保护的存储器区域的输入请求以及具有多个级别的计数器树结构。 此外，可以接受传入请求，并且可以确定是否根据对等树结构在每个级别的基础上挂起传入请求。

    SCALABLE MULTI-KEY MEMORY ENCRYPTION
    59.
    发明申请
    SCALABLE MULTI-KEY MEMORY ENCRYPTION 有权

    公开(公告)号：US20250053668A1

    公开(公告)日：2025-02-13

    申请号：US18929329

    申请日：2024-10-28

    Applicant: Intel Corporation

    Inventor： Barry E. Huntley ,  Hormuzd M. Khosravi ,  Thomas Toll ,  Ramya Jayaram Masti ,  Siddhartha Chhabra ,  Vincent Von Bokern

    IPC: G06F21/60 ,  G06F12/06 ,  H04L9/14

    Abstract: Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.

Patent Agency Ranking