公开(公告)号：US09836316B2

公开(公告)日：2017-12-05

申请号：US13631408

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F9/455 ,  G06F9/45 ,  G06F9/00

CPC classification number: G06F9/4552 ,  G06F8/44 ,  G06F9/45516 ,  G06F9/45533 ,  G06F9/45554 ,  Y02D10/26 ,  Y02D10/28

Abstract: Technologies for performing flexible code acceleration on a computing device includes initializing an accelerator virtual device on the computing device. The computing device allocates memory-mapped input and output (I/O) for the accelerator virtual device and also allocates an accelerator virtual device context for a code to be accelerated. The computing device accesses a bytecode of the code to be accelerated and determines whether the bytecode is an operating system-dependent bytecode. If not, the computing device performs hardware acceleration of the bytecode via the memory-mapped I/O using an internal binary translation module. However, if the bytecode is operating system-dependent, the computing device performs software acceleration of the bytecode.

公开(公告)号：US09830196B2

公开(公告)日：2017-11-28

申请号：US14833315

申请日：2015-08-24

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F9/52 ,  G06F11/36

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

公开(公告)号：US20160179586A1

公开(公告)日：2016-06-23

申请号：US14574300

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu ,  Sara S. Baghsorkhi ,  Albert Hartono ,  Robert Valentine

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F8/41 ,  G06F8/4451 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0828 ,  G06F12/0875 ,  G06F2212/452

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

Abstract translation: 本文描述的实施例使用受限制的事务存储器（RTM）指令来实现推测性的编译时间优化，其将在错误的猜测的情况下被硬件自动地回滚。 在一个实施例中，与用于执行SLE的常规RTM实现相比，描述了用于推测性编译器优化的轻量级RTM以提供较低的操作开销。

公开(公告)号：US09146844B2

公开(公告)日：2015-09-29

申请号：US13893238

申请日：2013-05-13

Applicant: INTEL CORPORATION

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：US20150160715A1

公开(公告)日：2015-06-11

申请号：US14594465

申请日：2015-01-12

Applicant: Intel Corporation

Inventor： Jaewoong Chung ,  Hanjun Kim ,  Youfeng Wu

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/30083 ,  G06F9/3836 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有核心的装置，其核心包括各自执行目标指令集架构（ISA）的指令的功能单元和功率控制器，以响应于功率识别领域来控制第一功能单元的功率模式 要在核心上执行的代码块的功率区域的功率指令。 描述和要求保护其他实施例。