公开(公告)号：US10957581B2

公开(公告)日：2021-03-23

申请号：US16451269

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027 ,  H01L21/3105

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US10943866B2

公开(公告)日：2021-03-09

申请号：US16661416

申请日：2019-10-23

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Michael Rizzolo ,  Christopher J. Penny ,  Huai Huang ,  Lawrence A. Clevenger ,  Hosadurga Shobha

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

公开(公告)号：US10830841B1

公开(公告)日：2020-11-10

申请号：US16445690

申请日：2019-06-19

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Lawrence A. Clevenger ,  Theodorus E. Standaert ,  James Stathis

IPC: G11C11/16 ,  G01R33/09 ,  H01L27/22

Abstract: A semiconductor device includes a device magnetic tunnel junction (MTJ) and sensor MTJs. A spin polarization of a free layer of the device MTJ is configurable based at least in part on electrical energy supplied to the device MTJ. A spin polarization of a corresponding free layer of each sensor MTJ is configurable based at least in part on a magnetic field created by the spin polarization of the free layer of the device MTJ. A circuit disposed is in electrical communication with the plurality of sensor MTJs and configured to determine the corresponding free layer spin polarizations of each of the sensor MTJs based at least in part on electrical energy supplied to the sensor MTJs by the circuit. The circuit is configured to determine a magnetoresistance of the device MTJ based at least in part on the determined corresponding free layer spin polarizations of the sensor MTJ.

公开(公告)号：US10734277B2

公开(公告)日：2020-08-04

申请号：US16194545

申请日：2018-11-19

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs ,  Brent Anderson

IPC: H01L21/768

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.

公开(公告)号：US20200227313A1

公开(公告)日：2020-07-16

申请号：US16245033

申请日：2019-01-10

Applicant: International Business Machines Corporation

Inventor： Kisik Choi ,  Koichi Motoyama ,  Ashim Dutta ,  Iqbal R. Saraf ,  Benjamin D. Briggs

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

公开(公告)号：US20200161175A1

公开(公告)日：2020-05-21

申请号：US16194545

申请日：2018-11-19

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs ,  Brent Anderson

IPC: H01L21/768

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.

公开(公告)号：US10658233B2

公开(公告)日：2020-05-19

申请号：US16163256

申请日：2018-10-17

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Benjamin D. Briggs ,  Gangadhara Raja Muthinti ,  Cornelius Brown Peethala ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

公开(公告)号：US20200051924A1

公开(公告)日：2020-02-13

申请号：US16659995

申请日：2019-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs

IPC: H01L23/544 ,  H01L27/22

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

公开(公告)号：US10515894B2

公开(公告)日：2019-12-24

申请号：US15966236

申请日：2018-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Michael Rizzolo ,  Nicole A. Saulnier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

公开(公告)号：US20190384180A1

公开(公告)日：2019-12-19

申请号：US16553854

申请日：2019-08-28

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Michael Rizzolo ,  Ekmini Anuja De Silva ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: G03F7/40 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/033 ,  G03F7/20 ,  H01L21/266 ,  H01L21/306

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.