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公开(公告)号：US20190318960A1
公开(公告)日：2019-10-17
申请号：US16451269
申请日：2019-06-25
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Michael Rizzolo , Terry A. Spooner , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L21/033 , H01L23/522 , H01L23/532 , H01L21/311 , H01L21/3105
摘要： A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
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公开(公告)号：US09997408B2
公开(公告)日：2018-06-12
申请号：US14872302
申请日：2015-10-01
IPC分类号： H01L21/00 , H01L21/768 , G06F17/50 , H01L21/66
CPC分类号： H01L21/76892 , G06F17/5036 , G06F17/5063 , G06F17/5072 , G06F17/5081 , H01L22/20
摘要： A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.
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公开(公告)号：US09831182B2
公开(公告)日：2017-11-28
申请号：US14966248
申请日：2015-12-11
发明人： Terry A. Spooner , Wei Wang , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/3213
CPC分类号： H01L23/53238 , H01L21/32136 , H01L21/76805 , H01L21/76814 , H01L21/76826 , H01L21/7684 , H01L21/76877 , H01L21/76883 , H01L23/53295
摘要： A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive material, the opening extending from a first surface to a second surface of the dielectric material layer and being in contact with a portion of the substrate; performing a plasma treatment process to chemically enrich exposed surfaces of the dielectric material that line the opening to form a chemically-enriched dielectric surface layer that included an element in a higher concentration than a remaining portion of the dielectric material layer; performing a chemical treatment process to remove a metal contact product from the portion of the substrate that is in contact with the opening; and disposing a conductive material in the opening to substantially fill the opening and form the interconnect structure.
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公开(公告)号：US09768113B2
公开(公告)日：2017-09-19
申请号：US15152981
申请日：2016-05-12
申请人： International Business Machines Corporation , Tokyo Electron Limited , STMicroelectronics, Inc.
发明人： Yannick Feurprier , Joe Lee , Lars W. Liebmann , Yann Mignot , Terry A. Spooner , Douglas M. Trickett , Mehmet Yilmaz
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528 , H01L23/532 , H01L21/033 , H01L21/311 , H01L21/321
CPC分类号： H01L23/5226 , H01L21/0332 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76877 , H01L21/76897 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.
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公开(公告)号：US20160379869A1
公开(公告)日：2016-12-29
申请号：US14749811
申请日：2015-06-25
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76814 , H01L21/76802 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L21/76888 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53266
摘要： A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.
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6.发明申请VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION 审中-公开通过使用边框图像平移过程确定横向尺寸的形式公开(公告)号：US20160358820A1
公开(公告)日：2016-12-08
申请号：US15239178
申请日：2016-08-17
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76811 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L23/5329
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
摘要翻译： 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。
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公开(公告)号：US11875987B2
公开(公告)日：2024-01-16
申请号：US17325509
申请日：2021-05-20
IPC分类号： H01L23/528 , H01L21/768 , H01L23/532 , H01L23/535 , H01L21/285 , H01L23/485
CPC分类号： H01L23/5283 , H01L21/28562 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/535 , H01L23/53266 , H01L23/5329 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257
摘要： A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.
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公开(公告)号：US11145543B2
公开(公告)日：2021-10-12
申请号：US16541448
申请日：2019-08-15
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
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公开(公告)号：US20210118732A1
公开(公告)日：2021-04-22
申请号：US16659717
申请日：2019-10-22
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
摘要： A method is presented for forming self-aligned vias by employing top level line double patterns. The method includes forming a plurality of first conductive lines within a first dielectric material, recessing one or more of the plurality of first conductive lines to define first openings, filling the first openings with a second dielectric material, and forming sacrificial blocks perpendicular to the plurality of first conductive lines. The method further includes forming vias directly underneath the sacrificial blocks, removing the sacrificial blocks, and constructing a plurality of second conductive lines such that the vias align to both the plurality of first conductive lines and the plurality of second conductive lines.
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公开(公告)号：US10886168B2
公开(公告)日：2021-01-05
申请号：US16430926
申请日：2019-06-04
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L23/532
摘要： Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.
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