公开(公告)号：US20240429098A1

公开(公告)日：2024-12-26

申请号：US18340301

申请日：2023-06-23

Applicant: International Business Machines Corporation

Inventor： Albert M. Chu ,  Ruilong Xie ,  Brent A. Anderson ,  Junli Wang ,  Jay William Strane ,  Leon Sigal ,  David Wolpert

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/06

Abstract: A semiconductor structure with two adjacent semiconductor devices of a plurality of semiconductor devices that have a backside contact that connects two adjacent source/drains of the two adjacent semiconductor devices to a backside power rail. The semiconductor provides the backside contact with a larger bottom contact area with the backside power rail than a combined contact area of the two top surfaces of the backside contact with the two adjacent source/drains.

公开(公告)号：US20240349631A1

公开(公告)日：2024-10-17

申请号：US18133304

申请日：2023-04-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  David Wolpert

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8833 ,  H10B63/34 ,  H10N70/021 ,  H10N70/826 ,  H10N70/841

Abstract: A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.

公开(公告)号：US20240203982A1

公开(公告)日：2024-06-20

申请号：US18069213

申请日：2022-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  David Wolpert ,  Takashi Ando

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/66181

Abstract: A logic cell includes a first trench capacitor disposed between and connecting a topside metal layer to a backside metal layer. The first trench capacitor includes an outer plate, connected to a first power rail on the backside metal layer, an inner plate, connected to a second power rail on backside metal layer, and an insulating layer separating the inner plate from the outer plate.

公开(公告)号：US20240096801A1

公开(公告)日：2024-03-21

申请号：US17932327

申请日：2022-09-15

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  David Wolpert ,  Lawrence A. Clevenger

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/5226

Abstract: Embodiments include super via placement in the development of an integrated circuit. Aspects of the invention include obtaining a power distribution network for the integrated circuit (IC) IC, wherein the PDN includes a plurality of metal vias each configured to connect adjacent metal layers of a plurality of metal layers. Aspects also include placing one or more cells on each metal layer of the IC and identifying a power demand associated with each of the one or more cells. Aspects further include updating the PDN, based on the power demand associated with each of the one or more cells, to replace at least two of the plurality of metal vias with a super via that is configured to connect non-adjacent metal layers of the plurality of metal layers.

公开(公告)号：US20240079294A1

公开(公告)日：2024-03-07

申请号：US17902428

申请日：2022-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Chih-Chao Yang ,  David Wolpert

IPC: H01L23/48 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.

公开(公告)号：US11916384B2

公开(公告)日：2024-02-27

申请号：US17479246

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Basanth Jagannathan ,  Michael Hemsley Wood ,  Leon Sigal ,  James Leland ,  Alexander Joel Suess ,  Benjamin Neil Trombley ,  Paul G. Villarrubia

IPC: G05B99/00 ,  H02J3/00

CPC classification number: H02J3/0073 ,  H02J3/003 ,  H02J3/004

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

公开(公告)号：US20230252218A1

公开(公告)日：2023-08-10

申请号：US17666635

申请日：2022-02-08

Applicant: International Business Machines Corporation

Inventor： BRIAN VERAA ,  Ryan Michael Kruse ,  Christopher Gonzalez ,  David Wolpert

IPC: G06F30/398

CPC classification number: G06F30/398

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

公开(公告)号：US11663391B2

公开(公告)日：2023-05-30

申请号：US17411113

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Ryan Michael Kruse ,  Leon Sigal ,  Richard Edward Serton ,  Matthew Stephen Angyal ,  Terence Hook ,  Richard Andre Wachnik

IPC: G06F30/394 ,  H01L27/02

CPC classification number: G06F30/394 ,  H01L27/0207

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

公开(公告)号：US20230048541A1

公开(公告)日：2023-02-16

申请号：US17401379

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： Brian Veraa ,  David Wolpert ,  Ryan Michael Kruse ,  Christopher Gonzalez

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/347 ,  G06F30/343

Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

公开(公告)号：US20220181252A1

公开(公告)日：2022-06-09

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.