公开(公告)号：US20220181442A1

公开(公告)日：2022-06-09

申请号：US17677859

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US11296229B2

公开(公告)日：2022-04-05

申请号：US16022494

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Yih Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Gilbert Dewey ,  Shriram Shivaraman ,  Matthew V. Metz

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.

公开(公告)号：US20220093596A1

公开(公告)日：2022-03-24

申请号：US17030346

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/092 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.

公开(公告)号：US11276691B2

公开(公告)日：2022-03-15

申请号：US16134824

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.

公开(公告)号：US20220059656A1

公开(公告)日：2022-02-24

申请号：US17453088

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US11257956B2

公开(公告)日：2022-02-22

申请号：US15942175

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van Le ,  Jack Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L21/425 ,  H01L29/66 ,  H01L29/423

Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.

公开(公告)号：US11251302B2

公开(公告)日：2022-02-15

申请号：US16640465

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US20220028861A1

公开(公告)日：2022-01-27

申请号：US17492487

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L27/108 ,  H01L25/065 ,  H01L23/64

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US20220028779A1

公开(公告)日：2022-01-27

申请号：US17493715

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11195919B2

公开(公告)日：2021-12-07

申请号：US16148621

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/04 ,  H01L29/165 ,  H01L27/12 ,  H01L27/092

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.