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    Nitride semiconductor substrate and method of manufacturing the same
    51.
    发明授权
    Nitride semiconductor substrate and method of manufacturing the same 有权
    氮化物半导体衬底及其制造方法

    公开(公告)号：US08785942B2

    公开(公告)日：2014-07-22

    申请号：US13352987

    申请日：2012-01-18

    申请人： Akira Yoshida ,  Jun Komiyama ,  Yoshihisa Abe ,  Hiroshi Oishi ,  Kenichi Eriguchi ,  Shunichi Suzuki

    发明人： Akira Yoshida ,  Jun Komiyama ,  Yoshihisa Abe ,  Hiroshi Oishi ,  Kenichi Eriguchi ,  Shunichi Suzuki

    IPC分类号： H01L29/15

    CPC分类号： H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7787

    摘要： A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse.In a nitride semiconductor substrate 10 having a substrate 1, a buffer layer 2 formed on one principal plane of the substrate 1, an intermediate layer 3 formed on the buffer layer 2, an electron transport layer 4 formed on the intermediate layer 3, and an electron supply layer 5 formed on the electron transport layer 4, the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5×1016 atoms/cm3 to 1×1018 atoms/cm3 and is of AlxGa1-xN (0.05≦x≦0.24), and the electron transport layer 4 has a thickness of 5 nm to 200 nm and is of AlyGa1-yN (0≦y≦0.04).

    摘要翻译： 提供了适用于常关型高击穿电压装置的氮化物半导体衬底和制造衬底的方法，其允许更高的阈值电压和电流崩溃的改善。 在具有衬底1的氮化物半导体衬底10中，形成在衬底1的一个主平面上的缓冲层2，形成在缓冲层2上的中间层3，形成在中间层3上的电子传输层4和 形成在电子输送层4上的电子供给层5，中间层3的厚度为200nm〜1500nm，碳浓度为5×1016原子/ cm3〜1×1018原子/ cm3，为AlxGa1-xN（ 0.05＆nlE; x＆lt; L; 0.24），电子传输层4的厚度为5nm〜200nm，为Al y Ga 1-y N（0＆nl E; y＆nlE; 0.04）。

    COMPOUND SEMICONDUCTOR SUBSTRATE
    55.
    发明申请
    COMPOUND SEMICONDUCTOR SUBSTRATE 有权
    化合物半导体基板

    公开(公告)号：US20110062556A1

    公开(公告)日：2011-03-17

    申请号：US12879035

    申请日：2010-09-10

    申请人： Jun KOMIYAMA ,  Kenichi Eriguchi ,  Hiroshi Oishi ,  Yoshihisa Abe ,  Akira Yoshida ,  Shunichi Suzuki

    发明人： Jun KOMIYAMA ,  Kenichi Eriguchi ,  Hiroshi Oishi ,  Yoshihisa Abe ,  Akira Yoshida ,  Shunichi Suzuki

    IPC分类号： H01L29/20

    CPC分类号： H01L21/0254 ,  H01L21/02458 ,  H01L21/02507

    摘要： A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6≦X≦1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1≦y≦0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlyGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

    摘要翻译： 一种禁止产生裂纹或翘曲的化合物半导体衬底，优选用于常闭型高击穿电压器件，其中AlxGa1-xN单晶层（0.6＆amp; NlE; X＆amp; NlE; 1.0 ）含有1×1018原子/ cm 3至1×1021原子/ cm3的碳和含有1×10 17原子/ cm 3至1×1021原子/ cm 3的碳的Al y Ga 1-y N单晶层（0.1＆lt; 1lE; y＆nlE; 0.5） 交替重复堆叠，并且在Si单晶衬底1上沉积具有碳浓度为5×10 17原子/ cm 3以下的电子传输层31和电子供给层32的氮化物活性层3 订购。 Al x Ga 1-x N单晶层21和Al y Ga 1-y N单晶层22的碳浓度分别从衬底1侧朝向上述有源层3侧减小。 以这种方式制造化合物半导体衬底。

    Substrate for compound semiconductor device and compound semiconductor device using the same
    58.
    发明申请
    Substrate for compound semiconductor device and compound semiconductor device using the same 审中-公开
    用于化合物半导体器件的衬底和使用其的化合物半导体器件

    公开(公告)号：US20070069216A1

    公开(公告)日：2007-03-29

    申请号：US11434115

    申请日：2006-05-16

    申请人： Jun Komiyama ,  Yoshihisa Abe ,  Shunichi Suzuki ,  Hideo Nakanishi

    发明人： Jun Komiyama ,  Yoshihisa Abe ,  Shunichi Suzuki ,  Hideo Nakanishi

    IPC分类号： H01L31/0312

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： A substrate for compound semiconductor device and a compound semiconductor device using the substrate are provided which allow a breakdown voltage to be high, cause little energy loss, and are suitably used for a high-electron mobility transistor etc. An n-type 3C—SiC single crystal buffer layer 3 having a carrier concentration of 1016-1021/cm3, a hexagonal GaxAl1-xN single crystal buffer layer (0≦x

    摘要翻译： 提供了一种化合物半导体器件的基板和使用该基板的化合物半导体器件，其允许击穿电压高，导致很少的能量损失，并且适合用于高电子迁移率晶体管等。n型3C-SiC 载流子浓度为10-16 / 21/3/3的单晶缓冲层3，六方晶系 > 1×1×N单晶缓冲层（0 <= x <1）4，n型六方晶系Al 1-y < 载流子浓度为10〜10/10/10/10以上的SUB> N单晶层（0.2 <= y <= 1）5 ，和n型六方晶系Al 1-z N单晶载体供给层（0≤z≤0.8,0.2≤yz≤1） ）6具有载流子浓度为10 11 -10 16 / cm 3的物质依次层叠在n型Si单晶衬底2上 具有晶面取向{111}和载体浓度为10 16 -10 21 / cm 3。 在上述基板2的背面形成有背面电极7，在上述载体供给层6的表面上形成有表面电极8。

    Semiconductor memory
    60.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4622655A

    公开(公告)日：1986-11-11

    申请号：US607026

    申请日：1984-05-04

    申请人： Shunichi Suzuki

    发明人： Shunichi Suzuki

    IPC分类号： G11C11/409 ,  G11C11/4099 ,  G11C11/24

    CPC分类号： G11C11/4099

    摘要： A semiconductor memory has at least a pair of bit lines, a plurality of word lines crossing the pair of bit lines, a pair of dummy word lines crossing the pair of bit lines, memory cells arranged at intersections between the bit lines and the word lines, dummy cells arranged at intersections between any the bit lines and the dummy word lines, a sense amplifier connected to the pair of bit lines, and a means for equalizing the potentials of the pair of bit lines. Each of the memory cell has a transistor and a capacitor. Each dummy cell has the same construction as each memory cell. The pair of bit lines and dummy cell capacitors are electrically connected at a predetermined timing and are set at a third voltage, the corresponding dummy cell is disconnected from one of the bit line pair, to which a selected memory cell capacitor is connected. Subsequently, a voltage difference between voltages on the bit lines is detected.

    摘要翻译： 半导体存储器具有至少一对位线，与该对位线交叉的多条字线，与该对位线交叉的一对虚拟字线，位于位线和字线之间的交叉处的存储单元 布置在任何位线和虚拟字线之间的交叉处的虚拟单元，连接到所述一对位线的读出放大器以及用于均衡所述一对位线的电位的装置。 每个存储单元具有晶体管和电容器。 每个虚拟单元具有与每个存储单元相同的结构。 一对位线和虚设单元电容器以预定的定时电连接并被设置为第三电压，相应的虚设单元与连接所选存储单元电容器的位线对之一断开。 随后，检测位线上的电压之间的电压差。