公开(公告)号：US20060049434A1

公开(公告)日：2006-03-09

申请号：US11219308

申请日：2005-09-02

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L29/80

CPC分类号： H01L29/42356 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n−-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

摘要翻译： 半导体器件及其制造方法包括其上选择性地形成氧化物膜的单晶硅衬底。 在氧化膜上形成栅极多晶硅。 栅极多晶硅的表面被栅极氧化膜覆盖，该栅极氧化物膜的表面被杂质浓度高于衬底的n型掺杂的阴极膜覆盖，作为n型 层。 在阴极膜中，与衬底接触的部分成为具有高杂质浓度的n + +缓冲区，接着形成p基区。 在p基区旁边，形成n + SUP源源区。 在阴极膜上，选择性地形成层间绝缘膜，在其上形成发射电极。 以高速率的可接受的产品获得诸如IGBT的半导体器件，具有优异的导通电压到关断损耗折衷和优良的导通电压对击穿电压的折衷。

公开(公告)号：US06610572B1

公开(公告)日：2003-08-26

申请号：US09722927

申请日：2000-11-27

申请人： Manabu Takei ,  Tatsuhiko Fujihira

发明人： Manabu Takei ,  Tatsuhiko Fujihira

IPC分类号： H01L21336

CPC分类号： H01L29/66712 ,  H01L21/263 ,  H01L29/32 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.

摘要翻译： 提供了一种半导体器件，其可以通过在晶片工艺中使用便宜的FZ晶片来制造，并且在反面的最外部分的高杂质浓度层和在反面的最外部处以及在相反侧的边界处仍然具有高杂质浓度的尖锐倾斜 高杂质浓度和低杂质浓度漂移层，从而实现低成本和高性能。 还提供了一种用于制造半导体器件的方法，即使在形成有源区和其电极之后，也可以在反面的最外部形成高杂质浓度缓冲层和高杂质浓度层，而没有任何明显的麻烦 在右侧，从而实现低成本和高性能。

公开(公告)号：US20130026560A1

公开(公告)日：2013-01-31

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US08138542B2

公开(公告)日：2012-03-20

申请号：US12427322

申请日：2009-04-21

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76 ,  H01L21/20

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US07863151B2

公开(公告)日：2011-01-04

申请号：US12489884

申请日：2009-06-23

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L21/76

CPC分类号： H01L29/66712 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66136 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

摘要翻译： 用于制造超结半导体器件的制造方法在表现出低电阻的n型半导体衬底上表现出高电阻的n型外延层上形成氧化物膜和氮化物膜。 划线区域中的氮化物膜的部分通过图案化而不被去除，并且通过氮化物膜打开取向标记。 在氧化物膜中打开沟槽图案之后，形成具有高纵横比的沟槽。 去除划线区域外部的氧化膜部分，将p型外延层埋设在沟槽中。 相对于氮化物膜研磨过度生长的p型外延层，通过蚀刻来完成研磨表面，露出n型外延层表面。

公开(公告)号：US07741192B2

公开(公告)日：2010-06-22

申请号：US11208459

申请日：2005-08-19

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L21/76

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。

公开(公告)号：US07601597B2

公开(公告)日：2009-10-13

申请号：US11855093

申请日：2007-09-13

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7811

摘要： A manufacturing method for a super-junction semiconductor device is disclosed. The method includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a base region(s) of the other conductivity type and source regions of the one conductivity type to be used for formation of MOS gate structures; a third step of forming, by anisotropic vapor-phase etching using an insulating film mask, trenches that penetrate through the base region(s) and reach the low-resistivity semiconductor substrate or its vicinity; and a fourth step of burying epitaxial layers of the other conductivity type in the respective trenches, the first to fourth steps being executed in this order.

摘要翻译： 公开了一种用于超结半导体器件的制造方法。 该方法包括：在一种导电类型的低电阻率半导体衬底上沉积至少一种将成为漂移层的一种导电类型的外延层的第一步骤; 形成用于形成MOS栅极结构的一种导电类型的另一导电类型的基极区域和源极区域的第二步骤; 通过使用绝缘膜掩模的各向异性气相蚀刻来形成穿过基极区域并到达低电阻率半导体衬底或其附近的沟槽的第三步骤; 以及在各个沟槽中埋入其他导电类型的外延层的第四步骤，第一至第四步骤依次执行。

公开(公告)号：US07499006B2

公开(公告)日：2009-03-03

申请号：US10794673

申请日：2004-03-05

申请人： Tomoyuki Shirasaki ,  Kazuhito Sato ,  Tsuyoshi Ozaki ,  Manabu Takei

发明人： Tomoyuki Shirasaki ,  Kazuhito Sato ,  Tsuyoshi Ozaki ,  Manabu Takei

IPC分类号： G09G3/30

CPC分类号： G09G3/32 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/027

摘要： A driver circuit for driving optical elements which is applied to a pixel driver circuit of the display device in this invention comprises a first current path with one end connected to the optical elements and the other end connected to a drive power supply; a second current path electrically connected to the first current path; a write-in control circuit which flows the write-in current having a predetermined current value in the direction of the other end side from the one end side of the first current path via the second current path; a charge storage circuit which stores the electric charge accompanying the write-in current flowing in the first current path; a drive control circuit which supplies the drive current to the optical elements via the first current path has a current value corresponding to the current value of the write-in current and drives these optical elements based on the electric charge stored in the charge storage circuit; and has a first timing operation in which the electric charge of the write-in current flowing in the first current path is stored by the write-in control circuit according to the write-in current in the charge storage circuit; and a second timing operation which supplies the drive current to the optical elements which does not overlap the time period of the first timing operation.

摘要翻译： 在本发明中，应用于显示装置的像素驱动电路的驱动光学元件的驱动电路包括：一端与光学元件连接的第一电流路径，与驱动电源连接的另一端; 电连接到所述第一电流路径的第二电流通路; 写入控制电路，其通过第二电流路径从第一电流路径的一端侧在另一端侧的方向上流过具有预定电流值的写入电流; 电荷存储电路，其存储伴随流过第一电流路径的写入电流的电荷; 通过第一电流路径将驱动电流提供给光学元件的驱动控制电路具有与写入电流的当前值相对应的电流值，并且基于存储在电荷存储电路中的电荷驱动这些光学元件; 并且具有第一定时操作，其中通过写入控制电路根据电荷存储电路中的写入电流来存储在第一电流路径中流动的写入电流的电荷; 以及第二定时操作，其将驱动电流提供给不与第一定时操作的时间段重叠的光学元件。

公开(公告)号：US20060186508A1

公开(公告)日：2006-08-24

申请号：US11397478

申请日：2006-04-04

申请人： Michio Nemoto ,  Manabu Takei ,  Tatsuya Naito

发明人： Michio Nemoto ,  Manabu Takei ,  Tatsuya Naito

IPC分类号： H01L23/58

CPC分类号： H01L29/0646 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/7395

摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

公开(公告)号：US20060076583A1

公开(公告)日：2006-04-13

申请号：US11219320

申请日：2005-09-02

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L29/80

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。