公开(公告)号：US20060076583A1

公开(公告)日：2006-04-13

申请号：US11219320

申请日：2005-09-02

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L29/80

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US08080846B2

公开(公告)日：2011-12-20

申请号：US11763625

申请日：2007-06-15

申请人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

发明人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/861

摘要： A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.

摘要翻译： 公开了一种提高平面型连接边缘端接结构的击穿电压的半导体器件。 该器件包括有源部分和边缘终止部分共同的n型半导体衬底层。 选择性地在有源部分的n型半导体衬底层上形成n型漂移区，并且在有源区中的n型半导体衬底层上选择性地形成p型分隔区。 在n型漂移区域和分隔区域上形成p型基体/体区。 源电极电连接到p型基体/体区。 在p型基体/半导体器件的划线面之间的边缘终端部形成p型分隔区域，使边缘终端部的p型分隔区域包围p型基极/ 身体区域。 漏电极与n型半导体衬底层电连接。

公开(公告)号：US07790519B2

公开(公告)日：2010-09-07

申请号：US11754751

申请日：2007-05-29

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/332

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US20070262362A1

公开(公告)日：2007-11-15

申请号：US11780624

申请日：2007-07-20

申请人： Setsuko WAKIMOTO ,  Manabu TAKEI ,  Shinji FUJIKAKE

发明人： Setsuko WAKIMOTO ,  Manabu TAKEI ,  Shinji FUJIKAKE

IPC分类号： H01L29/80

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

公开(公告)号：US20070224769A1

公开(公告)日：2007-09-27

申请号：US11754751

申请日：2007-05-29

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/331

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US06858500B2

公开(公告)日：2005-02-22

申请号：US10334127

申请日：2002-12-31

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

摘要翻译： 通过图案化同一多晶硅层形成TLPM的栅电极和平面器件的栅电极。 通过对相同的金属层进行构图，形成TLPM的漏极和源极，并且平面器件的漏电极和源电极形成。 因此，TLPM和平面器件可以通过所得的金属布线层和多​​晶硅层彼此电连接，而不需要在印刷电路板上进行引线接合。

公开(公告)号：US20080303087A1

公开(公告)日：2008-12-11

申请号：US12149016

申请日：2008-04-24

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US07262100B2

公开(公告)日：2007-08-28

申请号：US11219320

申请日：2005-09-02

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/336

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US20050087800A1

公开(公告)日：2005-04-28

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US07365392B2

公开(公告)日：2008-04-29

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/00

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

摘要翻译： 通过图案化同一多晶硅层形成TLPM的栅电极和平面器件的栅电极。 通过对相同的金属层进行构图，形成TLPM的漏极和源极，并且平面器件的漏电极和源电极形成。 因此，TLPM和平面器件可以通过所得的金属布线层和多​​晶硅层彼此电连接，而不需要在印刷电路板上进行引线接合。