Abstract:
A system and method of providing a micromirror pixel 400 that is highly resistant to bright failure states. The micromirror 400 uses an asymmetric yoke 402 to ensure the mirror is only attracted to the address electrode in one rotation direction. The landing mechanism on the other side of the torsion binge axis also is altered to allow the pixel to over rotate in the “off” direction. The over rotation ensures that light reflected by the mirror when in the off direction will miss the projection lens pupil, allowing the corresponding pixel to remain dark in both an operational and failed state.
Abstract:
A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the substrate. A hinge layer is spaced above the addressing layer by an air gap. A mirror layer is spaced over the hinge layer by a second air gap. The hinge layer has a hinge under and attached to the mirror, the hinge permitting the mirror to tilt. The hinge layer further has spring tips under the mirror, which are attached to the addressing layer. These spring tips provide a stationary landing surface for the mirror.
Abstract:
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.
Abstract:
A differential amplifier circuit used to test the underlying DRAM memory cells in large area spatial light modulator (SLM) arrays by significantly increasing the cell capacitance to bitline capacitance ratio. Since for these SLM devices it is not desirable to sub-divide the DRAM array into smaller test arrays in order to reduce the bitline capacitance, this invention addresses the bitline capacitance problem by reading the differential voltage between two adjacent cells rather than the actual voltage of each cell. The approach is to load, precharge, and readout a checkerboard pattern and then repeat the process for an inverse checkerboard pattern. Cell outputs which have the same value for the two complimentary patterns indicate a cell failure. In this approach, the cell differential voltage readout is effectively doubled to approximately ±200 mVolts, providing 100% test coverage of these large area arrays. This results in an effective DRAM test procedure which is independent of bitline capacitance.
Abstract:
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.
Abstract:
An improved memory cell (600) for use in a high-intensity light environment. The memory (600) comprises a substrate (616) capable of generating photocarriers when exposed to radiant energy, at least one transistor (602), at least one capacitor (604), and address node (610) electrically connecting the transistor (602) and the capacitor (604), and an active collector region (626). The active collector region (626) is fabricated in the substrate (616) in a position to allow the active collector region (626) to recombine photocarriers traveling through the substrate (616) thus preventing the photocarriers from reaching the address node (610).
Abstract:
A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.
Abstract:
A method of ejecting a drop of fluid includes providing a fluid ejector. The fluid ejector includes a substrate, a MEMS transducing member, a compliant membrane, walls, and a nozzle. The substrate includes a cavity and a fluidic feed. A first portion of the MEMS transducing member is anchored to the substrate. A second portion of the MEMS transducing member extends over at least a portion of the cavity and is free to move relative to the cavity. The compliant membrane is positioned in contact with the MEMS transducing member. A first portion of the compliant membrane covers the MEMS transducing member, A second portion of the compliant membrane being anchored to the substrate. Walls define a chamber that is fluidically connected to the fluidic feed. At least the second portion of the MEMS transducing member is enclosed within the chamber. A quantity of fluid is supplied to the chamber through the fluidic feed. An electrical pulse is applied to the MEMS transducing member to eject a drop of fluid through the nozzle.
Abstract:
A method of continuously ejecting liquid includes providing a liquid ejection system that includes a substrate and an orifice plate affixed to the substrate. Portions of the substrate define a liquid chamber. The orifice plate includes a MEMS transducing member that extends over at least a portion of the liquid chamber. A compliant membrane is positioned in contact with the MEMS transducing member. The compliant membrane includes an orifice. Liquid is provided under a pressure sufficient to eject a continuous jet of the liquid through the orifice located in the compliant membrane of the orifice plate by a liquid supply. A drop of liquid is caused to break off from the liquid jet by selectively actuating the MEMS transducing member which causes a portion of the compliant membrane to be displaced relative to the liquid chamber.
Abstract:
A method of ejecting liquid includes providing a liquid dispenser including a substrate and a diverter member. Portions of the substrate define a liquid supply channel and a liquid return channel. The diverter member includes a MEMS transducing member positioned in contact with a compliant membrane. The compliant membrane is anchored to the substrate such that the compliant membrane forms a portion of a wall of the liquid dispensing channel. A continuous flow of liquid is provided from a liquid supply through the liquid supply channel through the liquid dispensing channel through the liquid return channel and back to the liquid supply. The diverter member is selectively actuated to divert a portion of the liquid flowing through the liquid dispensing channel through outlet opening of the liquid dispensing channel when drop ejection is desired.