公开(公告)号：US07403875B2

公开(公告)日：2008-07-22

申请号：US11403554

申请日：2006-04-12

申请人： Christian Vogel ,  Dieter Draxelmayr

发明人： Christian Vogel ,  Dieter Draxelmayr

IPC分类号： G06F15/00

CPC分类号： H03M1/0836 ,  H03M1/1215

摘要： A signal processing system allows reconstruction of a non-uniformly sampled analog signal including sampling an analog signal at a sampling period of resulting in a quantized non-uniformly sampled signal. The non-uniformly sampled signal includes a sampled signal and an amplitude error between a signal sampled with the equidistant sample period and the non-uniformly sampled signal. A reconstructed amplitude error is determined through the time offset and the non-uniformly sampled signal, and is subtracted from the non-uniformly sampled signal. The signal processing system may be implemented in an electrocardiogram monitoring device or a mobile phone device.

摘要翻译： 信号处理系统允许重建非均匀采样的模拟信号，包括在采样周期采样模拟信号，得到量化的非均匀采样信号。 非均匀采样信号包括采样信号和采用等距采样周期采样的信号与非均匀采样信号之间的振幅误差。 通过时间偏移和非均匀采样的信号确定重建的振幅误差，并从不均匀采样的信号中减去。 信号处理系统可以在心电图监视装置或移动电话装置中实现。

公开(公告)号：US07365601B2

公开(公告)日：2008-04-29

申请号：US11114903

申请日：2005-04-25

申请人： Dieter Draxelmayr

发明人： Dieter Draxelmayr

IPC分类号： H03F3/04

CPC分类号： H03F3/45273

摘要： An amplifier for amplifying a signal which is applied to a signal input having a first pair of transistors (10), which is connected to the signal input and which contains two transistors (10-1, 10-2), currents flowing through the two transistors (10-1, 10-2) which have a specific operating current ratio (m) in relation to one another, a second pair of transistors (4), which is connected to the first pair of transistors (10) and which contains two transistors (4-1, 4-2), currents flowing through the two transistors (4-1, 4-2) which have the same operating current ratio (m) in relation to one another, and a signal output (3) of the amplifier (1) being provided between the first pair of transistors (10) and the second pair of transistors (4).

摘要翻译： 一种用于放大信号的放大器，其被施加到具有第一对晶体管（10）的信号输入端，所述第一对晶体管（10）连接到所述信号输入并且包含两个晶体管（10-1,10-2），流过所述两个晶体管 具有相对于彼此的比工作电流比（m）的晶体管（10-1,10-2），第二对晶体管（4），其连接到第一对晶体管（10）并且包含 两个晶体管（4-1,4-2），流过具有相对于相同工作电流比（m）的两个晶体管（4-1,4-2）的电流和信号输出（3） 所述放大器（1）设置在所述第一对晶体管（10）和所述第二对晶体管（4）之间。

公开(公告)号：US07352309B2

公开(公告)日：2008-04-01

申请号：US11392351

申请日：2006-03-29

申请人： Dieter Draxelmayr

发明人： Dieter Draxelmayr

IPC分类号： H03M1/00

CPC分类号： G11C27/02 ,  H03M1/0624 ,  H03M1/1215

摘要： A circuit arrangement for generating switch-on signals for driving track-and-hold elements of an analog-to-digital converter operating with interleaved timing comprises a first input for inputting a common reference clock signal, at least one window device for generating clock signals which are interleaved with respect to one another in terms of timing and whose respective time windows in which the respective of the clock signals has a first logic level are derived from the reference clock signal, and at least one gate device for generating a switch-on signal. The gate device is connected downstream of the window device and combines logically the reference clock signal with a respective of the clock signals and with a further information item so that a time window of the switch-on signal is at least longer than the window of the reference clock signal.

摘要翻译： 用于产生用于驱动以交错定时器操作的模数转换器的跟踪和保持元件的接通信号的电路装置包括用于输入公共参考时钟信号的第一输入端，用于产生时钟信号的至少一个窗口装置 它们在定时方面相互交错，并且其时钟信号具有第一逻辑电平的相应时间窗从参考时钟信号导出;以及至少一个门装置，用于产生接通 信号。 栅极器件连接在窗口器件的下游，并且逻辑地将参考时钟信号与相应的时钟信号和另外的信息项相结合，使得接通信号的时间窗口至少比窗口 参考时钟信号。

公开(公告)号：US07142143B2

公开(公告)日：2006-11-28

申请号：US11067602

申请日：2005-02-26

申请人： Dieter Draxelmayr

发明人： Dieter Draxelmayr

IPC分类号： H03M3/00

CPC分类号： H03M3/372 ,  H03M3/464

摘要： Time-continuous sigma/delta analog-to-digital converter for converting an analog input signal into a digital output signal (D), having at least one analog filter (3) which filters the analog input signal present at a signal input (2) of the analog filter (3), a quantizer (12) which is clocked by a clock signal (CLK) and quantizes the filtered analog signal, output by the analog filter (3), in order to generate the digital output signal (D), and having at least one reference capacitor (28) which can be continuously charged to a reference voltage (VREF) by a current source (31) for displacing a constant charge (Q) to/from the analog filter (3), such that no voltage jumps occur at the analog filter (3).

摘要翻译： 一种用于将模拟输入信号转换为数字输出信号（D）的时间连续的Σ/Δ模数转换器，具有至少一个模拟滤波器（3），其对存在于信号输入端（2）的模拟输入信号进行滤波， 模拟滤波器（3）的量化器（12），由时钟信号（CLK）计时并量化由模拟滤波器（3）输出的经滤波的模拟信号，以产生数字输出信号（D） ，并且具有至少一个参考电容器（28），其可以通过电流源（31）连续地充电到参考电压（V SUB REF），用于将恒定电荷（Q）移位到/ 模拟滤波器（3），使得在模拟滤波器（3）处不发生电压跳变。

公开(公告)号：US07135999B2

公开(公告)日：2006-11-14

申请号：US11067589

申请日：2005-02-26

申请人： Franz Kuttner ,  Christian Vogel ,  Dieter Draxelmayr

发明人： Franz Kuttner ,  Christian Vogel ,  Dieter Draxelmayr

IPC分类号： H03M1/06

CPC分类号： H03M1/0643 ,  H03M1/1215

摘要： A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlinearities (NL1, NL2) in the various analog/digital converters (15, 16) essentially compensate for one another.

摘要翻译： 一种电路装置（10），用于从具有不同定时运行的模拟/数字转换器（15,16）补偿非线性（NL 1，NL 2），具有至少两个模拟/数字转换器（15,16），每个模拟/数字转换器 不同的定时，并且每个都具有具有积分非线性（NL 1，NL 2）的预定的非线性转换器特性，并且其接受施加到电路装置上的输入端（11）的模拟输入信号（VIN），并分别将其转换为数字 中间信号（Z 1，Z 2）; 并且具有多路复用器（22），其布置在模/数转换器的下游，并且依次切换数字中间信号（Z 1，Z 2），以便从电路装置（10）产生数字输出信号（ZD） ）; 其中各个模拟/数字转换器（15,16）的非线性转换器特性中的至少一个被预先确定，使得在多路复用器（22）中已经将中间信号组合在一起之后，积分非线性（NL 1，NL 2） 各种模拟/数字转换器（15,16）基本上相互补偿。

公开(公告)号：US07126511B2

公开(公告)日：2006-10-24

申请号：US11064918

申请日：2005-02-24

申请人： Dieter Draxelmayr ,  Franz Kuttner ,  Christian Vogel

发明人： Dieter Draxelmayr ,  Franz Kuttner ,  Christian Vogel

IPC分类号： H03M1/00

CPC分类号： H03M1/0624 ,  H03M1/0836 ,  H03M1/1215

摘要： Circuit arrangement (1) for the delay adjustment of analog-to-digital converters (4-1, . . . 4-N, 504) operating in a temporally offset manner, having at least two analog-to-digital converters (4-1, . . . 4-N, 504) each having a signal path, which receive an analog signal (VI) present at an input (2) of the circuit arrangement (1) and in each case convert it into a digital intermediate signal (Z1, . . . ZN), the analog-to-digital converters (4-1, . . . 4-N, 504) in each case being clocked by clock signals (CLK1, . . . CLKN) which have a predetermined time offset with respect to one another; having a logic circuit (7), which interconnects the digital intermediate signals (Z1, . . . ZN) for the purpose of generating a digital output signal (ZD) of the circuit arrangement (1); it being possible to set the bandwidth of the signal paths of the analog-to-digital converters (4-1, . . . 4-N, 504) in each case in such a way that a deviation of the clock signal (CLK1, . . . CLKN) from the predetermined time offset for the respective analog-to-digital converter (4-1, . . . 4-N, 504) is compensated for by a change in the bandwidth of at least signal path.

摘要翻译： 用于以时间上偏移的方式工作的模数转换器（4-1，...，4，N，504）的延迟调整的电路装置（1），具有至少两个模拟 - 数字转换器（4 - 1，...，4，N，504），每个信号路径接收存在于电路装置（1）的输入端（2）的模拟信号（VI），并且在每种情况下都将其转换为数字中间信号 （Z 1，...，ZN），每个情况下的模数转换器（4-1，...，4，N，504）由时钟信号（CLK 1，...，CLKN） 相对于彼此的预定时间偏移; 具有用于产生电路装置（1）的数字输出信号（ZD）的数字中间信号（Z 1，...，ZN）互连的逻辑电路（7）。 在每种情况下，可以以这样的方式设置模数转换器（4-1，...，4，N，504）的信号路径的带宽，使得时钟信号（CLK 1 （...，...，CLKN）通过至少信号路径的带宽的变化来补偿来自相应的模数转换器（4-1，...，4，N，504）的预定时间偏移。

公开(公告)号：US20060097901A1

公开(公告)日：2006-05-11

申请号：US11244569

申请日：2005-10-06

申请人： Dieter Draxelmayr ,  Gernot Kubin ,  Christian Vogel

发明人： Dieter Draxelmayr ,  Gernot Kubin ,  Christian Vogel

IPC分类号： H03M1/12

CPC分类号： H03M1/1215

摘要： An arrangement for a time interleaved analog-to-digital converter that converts an signal to a digital signal and has a converter array with a plurality of analog-to-digital converters arranged in a fixed sequence in parallel with one another and can be operated with staggered timing with respect to one another is disclosed. The arrangement has a connection network which, for the purposes of actuation with staggered timing, generates in each case one control signal for an individual analog-to-digital converter in each case, with the connection network predefining the time sequence with which the control signals actuate the individual analog-to-digital converters in such a way that owing to this sequence of the control signals and thus the sequence of the actuated individual analog-to-digital converters there is at least a reduction in an interference spectrum in the spectrum of the input and/or output signal. A sorting method for operating this analog-to-digital converter is also disclosed.

公开(公告)号：US20050200506A1

公开(公告)日：2005-09-15

申请号：US11067589

申请日：2005-02-26

申请人： Franz Kuttner ,  Christian Vogel ,  Dieter Draxelmayr

发明人： Franz Kuttner ,  Christian Vogel ,  Dieter Draxelmayr

IPC分类号： H03M1/06 ,  H03M1/14 ,  H03M1/36

CPC分类号： H03M1/0643 ,  H03M1/1215

摘要： A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlinearities (NL1, NL2) in the various analog/digital converters (15, 16) essentially compensate for one another.

摘要翻译： 一种电路装置（10），用于从具有不同定时运行的模拟/数字转换器（15,16）补偿非线性（NL 1，NL 2），具有至少两个模拟/数字转换器（15,16），每个模拟/数字转换器 不同的定时，并且每个都具有具有积分非线性（NL 1，NL 2）的预定的非线性转换器特性，并且其接受施加到电路装置上的输入端（11）的模拟输入信号（VIN），并分别将其转换为数字 中间信号（Z 1，Z 2）; 并且具有多路复用器（22），其布置在模/数转换器的下游，并且依次切换数字中间信号（Z 1，Z 2），以便从电路装置（10）产生数字输出信号（ZD） ）; 其中各个模拟/数字转换器（15,16）的非线性转换器特性中的至少一个被预先确定，使得在多路复用器（22）中已经将中间信号组合在一起之后，积分非线性（NL 1，NL 2） 各种模拟/数字转换器（15,16）基本上相互补偿。

公开(公告)号：US20050194954A1

公开(公告)日：2005-09-08

申请号：US11045796

申请日：2005-01-28

申请人： Dieter Draxelmayr

发明人： Dieter Draxelmayr

IPC分类号： G05F3/16 ,  G05F3/26

CPC分类号： G05F3/265

摘要： Bandgap reference current source for generating a reference current (IREF) having: at least two bipolar transistors (T1, T2), the base terminals (B1, B2) of which are interconnected and connected to a fixed reference potential, the collector terminals (C1, C2) of which are connected to a collector current ratio setting circuit (15, 16), which sets a specific current ratio (m) between the two collector currents (IC1, IC2) flowing through the collector terminals (C1, C2), and the emitter terminals (E1, E2) of which are connected via a first resistor (RA) to a current node (13) which adds the emitter currents (IE1, IE2) flowing through the emitter terminals (E1, E2) to form a summation current (ISUM), which forms the reference current (IREF).

摘要翻译： 用于产生具有：至少两个双极晶体管（T 1，T 2 2）的参考电流（I SUB REF）的带隙参考电流源， 基极端子（B 1 SUB，B 2 2）互连并连接到固定的参考电位，集电极端子（C 1 C 1，C 2 （15,16）连接到集电极电流比设定电路（15,16），该集电极电流比设定电路设定两个集电极电流之间的比电流比（m） 流过集电极端子（C 1，C 2 2）的发射极端子（E 1/2） SUB，E 2 2）经由第一电阻器（R SUB）连接到电流节点（13），该电流节点（13）将发射极电流（I SUB） 流过发射极端子（E 1 1，E 2 2）以形成求和电流（I SUM ），其形成参考电流（I SUB> REF ）。

公开(公告)号：US20050190089A1

公开(公告)日：2005-09-01

申请号：US11064918

申请日：2005-02-24

申请人： Dieter Draxelmayr ,  Franz Kuttner ,  Christian Vogel

发明人： Dieter Draxelmayr ,  Franz Kuttner ,  Christian Vogel

IPC分类号： H03H7/12 ,  H03M1/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/10 ,  H03M1/12 ,  H03M1/14

CPC分类号： H03M1/0624 ,  H03M1/0836 ,  H03M1/1215

摘要： Circuit arrangement (1) for the delay adjustment of analog-to-digital converters (4-1, . . . 4-N, 504) operating in a temporally offset manner, having at least two analog-to-digital converters (4-1, . . . 4-N, 504) each having a signal path, which receive an analog signal (VI) present at an input (2) of the circuit arrangement (1) and in each case convert it into a digital intermediate signal (Z1, . . . ZN), the analog-to-digital converters (4-1, . . . 4-N, 504) in each case being clocked by clock signals (CLK1, . . . CLKN) which have a predetermined time offset with respect to one another; having a logic circuit (7), which interconnects the digital intermediate signals (Z1, . . . ZN) for the purpose of generating a digital output signal (ZD) of the circuit arrangement (1); it being possible to set the bandwidth of the signal paths of the analog-to-digital converters (4-1, . . . 4-N, 504) in each case in such a way that a deviation of the clock signal (CLK1, . . . CLKN) from the predetermined time offset for the respective analog-to-digital converter (4-1, . . . 4-N, 504) is compensated for by a change in the bandwidth of at least signal path.

摘要翻译： 用于以时间上偏移的方式工作的模数转换器（4-1，...，4，N，504）的延迟调整的电路装置（1），具有至少两个模拟 - 数字转换器（4 - 1，...，4，N，504），每个信号路径接收存在于电路装置（1）的输入端（2）的模拟信号（VI），并且在每种情况下都将其转换为数字中间信号 （Z 1，...，ZN），每个情况下的模数转换器（4-1，...，4，N，504）由时钟信号（CLK 1，...，CLKN） 相对于彼此的预定时间偏移; 具有用于产生电路装置（1）的数字输出信号（ZD）的数字中间信号（Z 1，...，ZN）互连的逻辑电路（7）。 在每种情况下，可以以这样的方式设置模数转换器（4-1，...，4，N，504）的信号路径的带宽，使得时钟信号（CLK 1 （...，...，CLKN）通过至少信号路径的带宽的变化来补偿来自相应的模数转换器（4-1，...，4，N，504）的预定时间偏移。