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    GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS
    51.
    发明申请
    GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS 有权
    集成电路中基于几何的电气检测

    公开(公告)号：US20110099529A1

    公开(公告)日：2011-04-28

    申请号：US12603594

    申请日：2009-10-22

    申请人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

    发明人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/16

    摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

    摘要翻译： 集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离 用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

    Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data
    55.
    发明申请
    Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data 失效
    通过使用测试者数据的空间相关性来确定故障模式的根本原因的方法

    公开(公告)号：US20080301597A1

    公开(公告)日：2008-12-04

    申请号：US11754947

    申请日：2007-05-29

    申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

    发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

    摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

    摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

    INTEGRATED CIRCUIT SELECTIVE SCALING
    58.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 有权
    集成电路选择性缩放

    公开(公告)号：US20060085768A1

    公开(公告)日：2006-04-20

    申请号：US10711959

    申请日：2004-10-15

    申请人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    发明人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    摘要翻译： 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

    Method of IC fabrication, IC mask fabrication and program product therefor
    59.
    发明申请
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US20050193363A1

    公开(公告)日：2005-09-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Integrated circuit logic with self compensating block delays
    60.
    发明申请
    Integrated circuit logic with self compensating block delays 有权
    具有自补偿块延迟的集成电路逻辑

    公开(公告)号：US20050189604A1

    公开(公告)日：2005-09-01

    申请号：US10787488

    申请日：2004-02-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    IPC分类号： H01L27/118 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H03K5/13

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。 这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。 从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。