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    Method of IC fabrication, IC mask fabrication and program product therefor
    1.
    发明申请
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US20050193363A1

    公开(公告)日：2005-09-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Integrated circuit logic with self compensating block delays
    2.
    发明授权
    Integrated circuit logic with self compensating block delays 有权
    具有自补偿块延迟的集成电路逻辑

    公开(公告)号：US07084476B2

    公开(公告)日：2006-08-01

    申请号：US10787488

    申请日：2004-02-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  David S. Kung ,  Daniel L. Ostapko

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  David S. Kung ,  Daniel L. Ostapko

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。 这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。 从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

    Method of IC fabrication, IC mask fabrication and program product therefor
    3.
    发明授权
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US07353492B2

    公开(公告)日：2008-04-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark A. Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark A. Lavin

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Integrated circuit logic with self compensating block delays
    4.
    发明申请
    Integrated circuit logic with self compensating block delays 有权
    具有自补偿块延迟的集成电路逻辑

    公开(公告)号：US20050189604A1

    公开(公告)日：2005-09-01

    申请号：US10787488

    申请日：2004-02-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    IPC分类号： H01L27/118 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H03K5/13

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。 这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。 从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

    Spatial correlation-based estimation of yield of integrated circuits
    8.
    发明授权
    Spatial correlation-based estimation of yield of integrated circuits 有权
    基于空间相关的集成电路产量估计

    公开(公告)号：US08276102B2

    公开(公告)日：2012-09-25

    申请号：US12718567

    申请日：2010-03-05

    申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

    发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

    摘要翻译： 提供了用于估计诸如大规模集成（VLSI）设计的集成电路设计的产量的技术。 一方面，用于确定VLSI查询设计的故障概率的方法包括以下步骤。 构建了一个Voronoi图，它包含一组代表设计的形状。 Voronoi图被转换为包括2t×2s矩形单元格的矩形网格，其中选择t和s，使得一个矩形单元格包含约一个至约五个Voronoi单元。 为网格中的每个单元格计算故障概率。 网格中的单元格成对合并。 重新计算合并的单元的故障概率，这说明了单元之间的空间相关性。 成对合并和重新计算步骤执行s + t次以确定设计失败的概率。

    Integrated circuit selective scaling
    10.
    发明授权
    Integrated circuit selective scaling 有权
    集成电路选择性缩放

    公开(公告)号：US07882463B2

    公开(公告)日：2011-02-01

    申请号：US12035572

    申请日：2008-02-22

    申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

    摘要翻译： 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。