INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
    53.
    发明申请
    INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL 有权
    集成电路,包括可编程逻辑和外部器件芯片允许超控

    公开(公告)号:US20080048716A1

    公开(公告)日:2008-02-28

    申请号:US11932901

    申请日:2007-10-31

    IPC分类号: H03K19/173

    摘要: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

    摘要翻译: 集成电路装置包括可编程逻辑块,监视输入,条件感测电路,耦合到所述监控输入并且被配置为响应于感测所述监视输入处的状况而在输出处产生状态感测信号,第一数字 输入,第一数字输出和门控电路,其配置在可编程逻辑块中并耦合在第一数字输入和第一数字输出之间。 门控电路具有耦合到条件感测电路并且产生输出的选通输入。 在不存在条件感测信号的情况下,该输出与第一数字输入的输入状态相关,并且在条件感测信号存在的情况下采用超驰状态。

    ESD protection structure for I/O pad subject to both positive and negative voltages
    56.
    发明授权
    ESD protection structure for I/O pad subject to both positive and negative voltages 有权
    I / O焊盘的ESD保护结构受到正和负电压的影响

    公开(公告)号:US07659585B2

    公开(公告)日:2010-02-09

    申请号:US12179243

    申请日:2008-07-24

    申请人: Gregory Bakker

    发明人: Gregory Bakker

    IPC分类号: H01L23/62

    CPC分类号: H01L27/0266

    摘要: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.

    摘要翻译: 公开了一种ESD保护电路,用于形成在三阱工艺的内部p阱中的n沟道MOS晶体管,并连接到根据本发明可以经历正和负电压的I / O焊盘。 如果I / O焊盘的电压为正,则第一开关将包含n沟道MOS晶体管的p阱连接到地,而第二开关将包含n沟道MOS晶体管的p阱连接到I / O焊盘 如果I / O焊盘的电压为负。 第三开关将n沟道MOS晶体管的栅极连接到p阱,如果它被截止,并且第四开关将n沟道MOS晶体管的栅极连接到Vcc,如果它是导通的。