公开(公告)号：US5481679A

公开(公告)日：1996-01-02

申请号：US121799

申请日：1993-09-15

申请人： Nobuo Higaki ,  Toshimichi Matsuzaki

发明人： Nobuo Higaki ,  Toshimichi Matsuzaki

IPC分类号： G06F13/36 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4027 ,  G06F13/28 ,  G06F15/7817

摘要： A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed. Hence, data throughput on the buses can be improved and the load capacity can be reduced, which leads to heightening of the clock frequency.

摘要翻译： 描述了一种数据处理装置，包括连接指令存储单元和指令准备单元的第一总线，连接指令执行单元和数据存储单元的第二总线，总线选择性地电连接和断开第一和第二总线， 以及控制单元，其响应于指令准备单元和指令执行单元的操作来控制总线开关的操作。 当通过总线开关连接第一和第二总线时，可以执行从指令准备单元到数据存储单元的访问以及从指令执行单元到指令存储单元的访问。 另一方面，当总线未连接时，可以同时执行从指令准备单元的指令和来自指令执行单元的数据访问。 因此，可以提高总线上的数据吞吐量，并且可以减小负载能力，从而导致时钟频率的提高。

公开(公告)号：USRE43729E1

公开(公告)日：2012-10-09

申请号：US13092453

申请日：2011-04-22

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令MCSST D1被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数0x0000_00FF进行比较。 极性判定单元23判断由积分结果寄存器6保持的值的第八位是否为ON。 复用器24输出由常数发生器21产生的最大值0x0000_00FF，由零发生器25产生的零值0x0000_0000和和积结果寄存器6的保持值到数据总线18之一。

公开(公告)号：US20100169614A1

公开(公告)日：2010-07-01

申请号：US12705300

申请日：2010-02-12

申请人： Shuichi TAKAYAMA ,  Nobuo Higaki

发明人： Shuichi TAKAYAMA ,  Nobuo Higaki

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/3853

摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1） 指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

公开(公告)号：US07362887B2

公开(公告)日：2008-04-22

申请号：US10965919

申请日：2004-10-18

申请人： Takahiro Oohashi ,  Naoaki Sumida ,  Nobuo Higaki

发明人： Takahiro Oohashi ,  Naoaki Sumida ,  Nobuo Higaki

IPC分类号： G06K9/00

CPC分类号： G06K9/00248 ,  G06K9/00234 ,  G06K9/00261

摘要： A face identification apparatus for identifying a face is designed to have a face region expectation measure for expecting his/her face region within the image; a pupil-candidate-point detection measure for converting the face region to an image of a standard size, making it a standard image, and detecting his/her right/left pupil candidate points out of a search region within the standard image; a reference data generation measure for generating a normalization image from the standard image with making it a standard a distance of the right/left pupil candidate points and making reference data for evaluating advisability of the face region from the normalization image; and a face region evaluation measure for obtaining a degree of approximation between the reference data and standard data prepared in advance and evaluating the advisability of the face region.

摘要翻译： 用于识别脸部的面部识别装置被设计为具有用于期望他/她的脸部区域在图像内的面部区域期望度量; 用于将脸部区域转换为标准尺寸的图像的瞳孔候选点检测措施，使其成为标准图像，并且从标准图像内的搜索区域检测他/她的右/左瞳孔候选点; 参考数据生成措施，用于从所述标准图像生成标准化图像，使其成为所述右/左瞳孔候选点的标准距离，并且从所述标准化图像中提取用于评估所述面部区域的可取性的参考数据; 以及面部区域评价措施，用于获得参考数据和预先准备的标准数据之间的近似度，并评估面部区域的可取性。

公开(公告)号：USRE39121E1

公开(公告)日：2006-06-06

申请号：US10366502

申请日：2003-02-13

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D 1”被解码时，积和结果寄存器6将其保持值输出到路径P 1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US6018796A

公开(公告)日：2000-01-25

申请号：US825479

申请日：1997-03-28

申请人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

发明人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3867

摘要： A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

摘要翻译： 数据处理器包括一个处理单元，处理流水线阶段的指令，其数量可在n和m之间切换，m是比n大的数字。 数据处理器还包括用于在n和m之间切换处理单元的流水线级数的切换单元。 切换单元包括指示单元，用于指示数据处理器是处于第一操作状态还是处于第二操作状态，这取决于为数据处理器提供的操作时钟的频率或提供给数据处理器的电源电压 处理器和流水线控制单元，用于在第一操作条件下命令处理单元在n个阶段中操作，并且用于在第二操作条件下命令处理单元以m级操作。

公开(公告)号：US5974540A

公开(公告)日：1999-10-26

申请号：US980676

申请日：1997-12-01

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/49921

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000-00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24输出由常数发生器21产生的最大值“0x0000-00FF”，由零发生器25产生的零值“0x0000-0000”和和积结果寄存器6的保持值之一 数据总线18。

公开(公告)号：US5850551A

公开(公告)日：1998-12-15

申请号：US588051

申请日：1996-01-22

申请人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3804 ,  G06F8/447 ,  G06F9/325

摘要： A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. A processor comprises: a pipeline comprising: an instruction fetching unit, an instruction decoding unit, and an executing unit; a branch target storage unit; a branch target registering unit for, after the instruction decoding unit has decoded a first loop exclusive instruction, registering branch target information of an instruction succeeding to the first loop exclusive instruction in the branch target registering unit; and a branch executing unit for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage unit, and controlling the pipeline so that the program executes the loop using the read branch target information.

摘要翻译： 编译器包括一个用于提取循环信息的循环检测单元和一个生成第一循环专用指令的高速循环应用单元，在循环进入之前立即进行指令，产生第二循环专用指令，并将指令置于 每个地方分支到循环的入口。 一种处理器，包括：流水线，包括：指令获取单元，指令解码单元和执行单元; 分支目标存储单元; 分支目标登记单元，用于在所述指令解码单元解码了第一循环专用指令之后，将在所述分支目标登记单元中的所述第一循环专用指令之后的指令的分支目标信息注册; 以及分支执行单元，用于在解码单元解码了第二循环专用指令之后，判断是否执行循环，如果判断执行，读取登记在分支目标存储单元中的分支目标信息，并且控制流水线，使得 该程序使用读分支目标信息执行循环。

公开(公告)号：US5748970A

公开(公告)日：1998-05-05

申请号：US640082

申请日：1996-04-30

申请人： Shinya Miyaji ,  Nobuo Higaki

发明人： Shinya Miyaji ,  Nobuo Higaki

IPC分类号： G06F9/48 ,  G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding to an interrupt level of an interrupt request signal, in sequential areas; a start address hold unit for holding start addresses, which can be updated, of the interrupt processing programs; a level hold unit for holding an interrupt level, which can be updated, of each interrupt signal inputted from the I/O devices; an interrupt reception unit for, when at least one of the interrupt signals is inputted, receiving an interrupt signal of a highest interrupt level out of the inputted interrupt signals and outputting an interrupt request signal of the same interrupt level; and a control unit for controlling a branch, when the interrupt request signal is outputted, by fetching one of the start addresses which corresponds to the interrupt level of the interrupt request signal from the start address hold unit and setting the start address in the program counter.

摘要翻译： 一种包括I / O设备和处理器核心的嵌入式微型计算机的中断控制装置，包括：程序存储单元，用于在顺序区域中存储每个对应于中断请求信号的中断级别的中断处理程序; 开始地址保持单元，用于保持中断处理程序的可更新的起始地址; 电平保持单元，用于保持从I / O设备输入的每个中断信号的可更新的中断电平; 中断接收单元，当输入至少一个中断信号时，从所输入的中断信号中接收到最高中断电平的中断信号，并输出相同中断电平的中断请求信号; 以及控制单元，用于当输出中断请求信号时，通过从起始地址保持单元中取出与中断请求信号的中断电平相对应的起始地址中的一个并在程序计数器中设置起始地址来控制分支 。

公开(公告)号：US08228214B2

公开(公告)日：2012-07-24

申请号：US12844134

申请日：2010-07-27

申请人： Yuya Shigenobu ,  Motokazu Ozawa ,  Nobuo Higaki ,  Takeshi Furuta ,  Takahiro Kageyama ,  Masaki Minami

发明人： Yuya Shigenobu ,  Motokazu Ozawa ,  Nobuo Higaki ,  Takeshi Furuta ,  Takahiro Kageyama ,  Masaki Minami

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  G10L19/167 ,  H04N19/44 ,  H04N19/91

摘要： A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

摘要翻译： 对比特流解码的可变长度码解码装置包括：存储单元，存储可变长度码表; 比特流缺口单元，输出固定长度的比特串; 参考单元，其参考存储单元输出解码数据和代码长度; 确定单元，确定是否累积了固定长度的比特串; 确定单元，其确定是否累积了长于所述固定长度的长度的比特串; 以及选择单元，其从所述确定单元中选择所述确定结果之一。 比特流切断单元基于所选择的确定结果设置起始位，并且选择单元从确定单元切换确定结果的选择。