公开(公告)号：US5545972A

公开(公告)日：1996-08-13

申请号：US301868

申请日：1994-09-06

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： G05F3/26 ,  G05F3/16

CPC分类号： G05F3/26

摘要： A current mirror includes first and second transistors each having a control terminal and a load path with two terminals. The control terminals of the first and second transistors and one of the terminals of the load path of the first transistor receive a first input current. Third, fourth and fifth transistors each have a control terminal and a load path with two terminals. The control terminals of the third, fourth and fifth transistors and one of the terminals of the load path of the third transistor receive a second input current of equal magnitude to the first input current. One of the terminals of the load path of the fifth transistor supplies an output current proportional to the two input currents. The other of the terminals of the load paths of the third and fifth transistors are each connected to one terminal of the load path of a respective one of the fourth and second transistors. The other of the terminals of the load paths of the first, second and fourth transistors are connected to a common reference point.

摘要翻译： 电流镜包括第一和第二晶体管，每个具有控制端和具有两个端子的负载路径。 第一晶体管的控制端和第一晶体管的负载路径的端子之一接收第一输入电流。 第三，第四和第五晶体管每个具有控制端子和具有两个端子的负载路径。 第三，第四和第五晶体管的控制端和第三晶体管的负载路径的端子之一接收与第一输入电流相等大小的第二输入电流。 第五晶体管的负载路径的端子之一提供与两个输入电流成比例的输出电流。 第三和第五晶体管的负载路径的另一个端子分别连接到第四和第二晶体管的相应一个的负载路径的一个端子。 第一，第二和第四晶体管的负载路径的另一个端子连接到公共参考点。

公开(公告)号：US08704541B2

公开(公告)日：2014-04-22

申请号：US13308569

申请日：2011-12-01

申请人： Bret Dale ,  Oliver Kiehl

发明人： Bret Dale ,  Oliver Kiehl

IPC分类号： G01R31/00

CPC分类号： G01R31/2889 ,  G01R31/2884

摘要： A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad.

摘要翻译： 公开了一种电路测试接口和测试方法。 电路测试接口可以包括测试电流传输焊盘，测试电压测量焊盘和包括输出端子的至少一个驱动电路。 至少一个驱动电路的输出端可以耦合到穿硅通孔（TSV）。 电路测试接口还可以包括耦合到（1）驱动电路的输出端，（2）测试电流传输焊盘和（3）测试电压测量板的至少一个开关模块。

公开(公告)号：US08704529B2

公开(公告)日：2014-04-22

申请号：US13253061

申请日：2011-10-04

申请人： Bret Dale ,  Oliver Kiehl

发明人： Bret Dale ,  Oliver Kiehl

IPC分类号： G01R1/00

CPC分类号： G01R31/3172 ,  G01R31/318572

摘要： A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.

摘要翻译： 公开了电路测试接口和测试方法。 电路测试接口可以包括测试电压输入焊盘，测试电压输出焊盘和多个输入缓冲器。 多个输入缓冲器中的每一个可以具有第一输入端子，第二输入端子和输出端子。 每个相应输入缓冲器的第一输入端可以耦合到多个穿硅通孔（TSV）中的一个。 电路测试接口还可以包括多个开关单元。 多个开关单元中的每一个可以具有第一端子和第二端子。 电路测试接口还可以包括耦合到多个输入缓冲器中的每一个的输出端和测试电压输出焊盘两者的扫描链。

公开(公告)号：US20070178864A1

公开(公告)日：2007-08-02

申请号：US11345422

申请日：2006-02-01

申请人： Oliver Kiehl ,  Katja Kienzl

发明人： Oliver Kiehl ,  Katja Kienzl

IPC分类号： H04B1/18 ,  G06F12/00

CPC分类号： G06F13/385

摘要： An electronic subsystem assembly including a subsystem circuit, a contact interface, a memory circuit, and a radio frequency interface. The subsystem circuit is configured to provide a system function. The contact interface is configured to receive input signals and output signals. The memory circuit is configured to receive the input signals via the contact interface and to transmit the output signals via the contact interface. The radio frequency interface is configured to receive data signals from the memory circuit and to provide a radio frequency transmission that includes the data signals.

摘要翻译： 包括子系统电路，接触接口，存储器电路和射频接口的电子子系统组件。 子系统电路被配置为提供系统功能。 触点界面配置为接收输入信号和输出信号。 存储器电路被配置为经由接触接口接收输入信号并且经由接触接口传送输出信号。 无线电频率接口被配置为从存储器电路接收数据信号并提供包括数据信号的射频传输。

公开(公告)号：US20070094554A1

公开(公告)日：2007-04-26

申请号：US11253716

申请日：2005-10-20

申请人： Martin Versen ,  Oliver Kiehl

发明人： Martin Versen ,  Oliver Kiehl

IPC分类号： G11C29/00

CPC分类号： G11C29/46 ,  G11C5/04 ,  G11C2029/4402

摘要： A test mode for component-specific testing of a memory module. Data is written to and stored in each memory component of a memory module, which data indicates whether the memory component is to execute a particular test mode. Upon receiving a test mode command supplied in common to all of the memory components on the memory module, each memory component examines the data to determine whether it is to execute a test mode command supplied contemporaneously therewith or subsequently supplied test mode commands.

摘要翻译： 用于内存模块组件特定测试的测试模式。 将数据写入并存储在存储器模块的每个存储器组件中，该数据指示存储器组件是否要执行特定的测试模式。 在接收到对存储器模块中的所有存储器组件共同提供的测试模式命令时，每个存储器组件检查数据以确定是否执行与其同时提供的测试模式命令或随后提供的测试模式命令。

公开(公告)号：US07060529B2

公开(公告)日：2006-06-13

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/50 ,  H01L21/30

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06937058B2

公开(公告)日：2005-08-30

申请号：US10620989

申请日：2003-07-16

申请人： Hans-Heinrich Viehmann ,  Oliver Kiehl

发明人： Hans-Heinrich Viehmann ,  Oliver Kiehl

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0298

摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

公开(公告)号：US06927709B2

公开(公告)日：2005-08-09

申请号：US10196676

申请日：2002-07-16

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L25/49 ,  H03M7/00 ,  H03M7/20

CPC分类号： H04L25/4908 ,  H04L7/0066 ,  H04L25/4904

摘要： An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word to obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.

摘要翻译： 从在M位线上接收的M位代码产生N比特字，M大于N，M比特码至少包括一个M比特码字和一个前一个M比特码字， 所述M位码字在至少两个位位置包括不同电平，并且所述先前的M位码字包括与相应位位置处的不同电平相反的电平，通过比较M-位码字的两位位置处的电平， 比特码字以获得第一值，比较前一M比特码字的两个对应比特位置处的电平以获得第二值，检测第一值与第二值相反，并且解码M位 响应于检测到第一值与第二值相反的代码字。 本发明的优点在于，所有参与变速器的线路具有相同的电特性，相同的含义和相同种类的负载。

公开(公告)号：US20050111275A1

公开(公告)日：2005-05-26

申请号：US10967899

申请日：2004-10-18

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

摘要翻译： 存储器件包括一对补充位线，包括第一位线和第二位线。 位线预充电块耦合在第一位线和第二位线之间。 读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。 读出放大器预充电块可以独立于位线预充电块来激活。 隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

公开(公告)号：US20050001298A1

公开(公告)日：2005-01-06

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/8242 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L27/105 ,  H01L23/544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。