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公开(公告)号：US07019554B2
公开(公告)日：2006-03-28
申请号：US10727106
申请日：2003-12-03
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.
摘要翻译： 集成电路包括至少一个可操作以执行一个或多个功能的主电路313。 至少一个终端节点DQ接收或发送操作信号。 有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。 至少一个终端节点耦合到第一和第二晶体管之间的公共节点。 控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。 或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。
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公开(公告)号：US06937058B2
公开(公告)日：2005-08-30
申请号：US10620989
申请日：2003-07-16
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.
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公开(公告)号：US20050122130A1
公开(公告)日：2005-06-09
申请号：US10727106
申请日：2003-12-03
IPC分类号： H03K19/003 , H04L25/02
CPC分类号： H04L25/0298
摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.
摘要翻译： 集成电路包括至少一个可操作以执行一个或多个功能的主电路313。 至少一个终端节点DQ接收或发送操作信号。 有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。 至少一个终端节点耦合到第一和第二晶体管之间的公共节点。 控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。 或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。
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公开(公告)号：US20050012519A1
公开(公告)日：2005-01-20
申请号：US10620989
申请日：2003-07-16
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.
摘要翻译： 一种集成电路，包括：可操作以执行一个或多个功能的至少一个主电路，并且包括用于接收或发送操作信号的至少一个I / O节点; 有源终端电路具有相同类型的第一和第二MOSFET串联耦合跨越第一源电位的Vdd节点和第二源电位的Vss节点，所述至少一个I / O节点耦合到公共节点之间 第一和第二MOSFET; 以及控制电路，其可操作以偏置第一和第二MOSFET，使得它们在公共节点处呈现受控阻抗。
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5.发明授权Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译： 集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二 电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡 耦合到第二晶体管的源极和漏极的电容。
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公开(公告)号：US20060104136A1
公开(公告)日：2006-05-18
申请号：US10988787
申请日：2004-11-15
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译： 包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。 位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。 在感测存储单元的电阻的初始时段期间，该开关能够导通。 位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。 所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。
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7.发明授权Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption 有权用于将差分模式信号转换成具有降低待机电流消耗的单端信号的电路公开(公告)号：US06819142B2
公开(公告)日：2004-11-16
申请号：US10387733
申请日：2003-03-13
IPC分类号： H03K1920
CPC分类号： H03K19/018528 , H03K19/0016
摘要： An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.
摘要翻译： 一种用于将差分模式信号转换成具有降低的功耗的单端信号的装置。 优选实施例包括单端转换器（例如，单端转换器505）和输出晶体管（例如，输出晶体管524），当单端转换器505处于待机状态时，可以将单端转换器505的输出 到一个已知的逻辑状态（如高逻辑或低逻辑）。 单端缓冲器（反相或非反相）可用于输出信号兼容性转换。
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公开(公告)号：US07573328B2
公开(公告)日：2009-08-11
申请号：US11670173
申请日：2007-02-01
IPC分类号： H03F3/38
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/03 , H03F2200/33 , H03F2200/351 , H03F2200/372
摘要： A power amplifier is disclosed. In one embodiment, the power amplifier is a Class-D Amplifier having a differential pulse width modulator is disclosed. The differential pulse width modulator has an input for receiving an input signal, a first output for outputting a first signal and a second output for outputting a second signal. A difference between the first signal and the second signal represents the pulse modulated signal. The differential pulse width modulator further has a comparator for comparing the first and second output signals. The comparator switches both the first and second output signal from a high state to a low state, if both the first and second output signals are in a high state.
摘要翻译： 公开了功率放大器。 在一个实施例中，功率放大器是具有差分脉冲宽度调制器的D类放大器。 差分脉冲宽度调制器具有用于接收输入信号的输入，用于输出第一信号的第一输出和用于输出第二信号的第二输出。 第一信号和第二信号之间的差表示脉冲调制信号。 差分脉冲宽度调制器还具有用于比较第一和第二输出信号的比较器。 如果第一和第二输出信号都处于高状态，比较器将第一和第二输出信号从高状态切换到低状态。
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公开(公告)号：US20080186089A1
公开(公告)日：2008-08-07
申请号：US11670173
申请日：2007-02-01
IPC分类号： H03F3/38
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/03 , H03F2200/33 , H03F2200/351 , H03F2200/372
摘要： A power amplifier is disclosed. In one embodiment, the power amplifier is a Class-D Amplifier having a differential pulse width modulator is disclosed. The differential pulse width modulator has an input for receiving an input signal, a first output for outputting a first signal and a second output for outputting a second signal. A difference between the first signal and the second signal represents the pulse modulated signal. The differential pulse width modulator further has a comparator for comparing the first and second output signals. The comparator switches both the first and second output signal from a high state to a low state, if both the first and second output signals are in a high state.
摘要翻译： 公开了功率放大器。 在一个实施例中，功率放大器是具有差分脉冲宽度调制器的D类放大器。 差分脉冲宽度调制器具有用于接收输入信号的输入，用于输出第一信号的第一输出和用于输出第二信号的第二输出。 第一信号和第二信号之间的差表示脉冲调制信号。 差分脉冲宽度调制器还具有用于比较第一和第二输出信号的比较器。 如果第一和第二输出信号都处于高状态，比较器将第一和第二输出信号从高状态切换到低状态。
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10.发明申请公开(公告)号：US20050157546A1
公开(公告)日：2005-07-21
申请号：US10758449
申请日：2004-01-15
CPC分类号： G11C11/16
摘要： The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.
摘要翻译： 在开始磁存储单元的写操作之前，MRAM器件的写入路径被预充电，增加了写操作的速度并减小了写周期时间。 参考线是预充电的，可以更好地控制字线和位线写入脉冲，从而缩短上升时间。 预充电时间可以隐藏在地址解码时间或冗余评估时间内。 本文还描述了用于全局参考电流发生器的电路设计。 还公开了一种快速接通电路，其增加对参考线预充电的速度。
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