公开(公告)号：US07903446B2

公开(公告)日：2011-03-08

申请号：US12401184

申请日：2009-03-10

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C5/063 ,  H01L27/11504 ,  H01L27/11507

摘要： A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.

摘要翻译： 存储器包括铁电电容器; 每个单体晶体管包括连接到每个铁电电容器的一个电极的漏极和连接到该字线的栅极; 以及包括复位晶体管，块选择晶体管和包括铁电电容器和单元晶体管的存储单元的存储单元块，其中单元晶体管的源极连接到板极线，强电介质电容器的另一个电极连接到 子位线之一，块选择晶体管的源极和漏极连接到子位线之一和位线中的一个，复位晶体管的源极连接到板线之一或 每个存储单元块中的复位晶体管的固定电位和漏极连接到一个子位线，并且存储单元块配置存储单元阵列。

公开(公告)号：US07852142B2

公开(公告)日：2010-12-14

申请号：US12250121

申请日：2008-10-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.

摘要翻译： 放大电路接收比较器的输出。 输出提供给第一，第二和第三晶体管的每个栅极。 第一和第二电阻串联连接。 第一和第二电阻器和第一二极管连接到第一晶体管的漏极。 第二个二极管并联连接。 第二二极管连接到第三电阻器的一端。 第三电阻器的另一端连接到第二晶体管的漏极。 第四和第五电阻串联连接。 第四电阻器的一端连接到第二晶体管的漏极。 比较器接收分别从第一和第二电阻器之间的连接节点获得的第一和第二反馈电压以及第四和第五电阻器之间的连接节点。 第三晶体管的漏极输出参考电压。

公开(公告)号：US07791922B2

公开(公告)日：2010-09-07

申请号：US12186088

申请日：2008-08-05

申请人： Sumiko Doumae ,  Daisaburo Takashima

发明人： Sumiko Doumae ,  Daisaburo Takashima

IPC分类号： G11C11/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.

摘要翻译： 半导体存储器件包括存储单元阵列，每个存储单元包括单元晶体管和铁电电容器; 感测放大器电路，用于通过一对位线来感测/放大从铁电电容器读出的信号; 一对去耦晶体管，设置在该对位线上以去耦合位线; 控制电路，用于向去耦晶体管的栅极提供控制信号，以控制去耦晶体管的导通; 以及与去耦晶体管和感测放大器电路之间的一对位线中的至少一个相关联地设置的虚拟电容器。 控制电路被配置为能够在读取开始之后经过一段时间后，使去耦晶体管从导通断开。

公开(公告)号：US20100090727A1

公开(公告)日：2010-04-15

申请号：US12563980

申请日：2009-09-21

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03K5/153 ,  H03K5/00

CPC分类号： H03K17/223 ,  H03K5/153

摘要： A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates.

摘要翻译： 本发明的电压检测电路包括NMOS晶体管二极管连接，其栅极和漏极被提供有电源电压，连接在NMOS晶体管的源极和接地电位之间的电阻和源电压检测 接收源的电压的电路，其中使用NMOS型晶体管作为NMOS晶体管，NMOS晶体管的沟道宽度和沟道长度被设置为使得在所述NMOS晶体管的VG-ID曲线上的工作点 NMOS型晶体管可以到达某一点，在某一点，即使温度波动，NMOS型晶体管的漏极电流恒定。

公开(公告)号：US07679412B2

公开(公告)日：2010-03-16

申请号：US12239188

申请日：2008-09-26

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G11C5/143 ,  G11C5/147

摘要： According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal.

摘要翻译： 根据本发明的一个方面，提供一种电源电路，包括：检测电路，其连接到外部电源电压，并且输出指示外部电源电压是否处于丢弃状态的第一信号 外部电源电压降低到参考电压以下; 控制电路，包括：延迟电路，其输出通过将所述第一信号延迟参考时间获取的第二信号; 以及确定电路，其基于所述第一信号和所述第二信号输出第三信号; 生成电路，其从所述外部电源电压产生内部电源电压，并且提供所述内部电源电压; 以及中断电路，其基于所述第三信号中断从所述发电电路提供的内部电源电压。

公开(公告)号：US20100020587A1

公开(公告)日：2010-01-28

申请号：US12505820

申请日：2009-07-20

申请人： Sumiko DOUMAE ,  Daisaburo Takashima

发明人： Sumiko DOUMAE ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/06 ,  G11C5/14 ,  G11C5/06

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5002

摘要： A ferroelectric memory is provided with a voltage generating circuit configured to generate prescribed driving potential, a driving interconnection to which the driving potential is applied, a plurality of memory cells connected to the driving interconnections and an internal voltage comparison circuit configured to compare inputted potential and to output results thereof. A plurality of voltage monitoring interconnections are provided to connect between a portion of the driving interconnection disposed at a position distant from the voltage generating circuit on the substrate and the internal voltage comparison circuit. The internal voltage comparison circuit compares potential inputted through the voltage monitoring interconnection with the driving potential.

摘要翻译： 铁电存储器设置有电压产生电路，其被配置为产生规定的驱动电位，施加驱动电位的驱动互连，连接到驱动互连的多个存储单元，以及内部电压比较电路，被配置为将输入的电位和 输出结果。 提供多个电压监视互连以连接布置在远离衬底上的电压产生电路的位置处的驱动互连部分和内部电压比较电路之间。 内部电压比较电路将通过电压监视互连输入的电位与驱动电位进行比较。

公开(公告)号：US20100011260A1

公开(公告)日：2010-01-14

申请号：US12513860

申请日：2007-11-28

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

IPC分类号： G11C29/04 ,  G06F11/22 ,  G06F11/00

CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

公开(公告)号：US07589513B2

公开(公告)日：2009-09-15

申请号：US11783039

申请日：2007-04-05

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147 ,  G11C7/04

摘要： A reference voltage generator circuit comprises a first current path and a second current path. The first current path is formed between an input terminal supplied with a first reference voltage and an output terminal and including a first diode and a first resistor serially connected from the input terminal. The second current path is formed between the input terminal and the output terminal and including a second diode, a second resistor and a third resistor serially connected from the input terminal. A comparator is supplied with a voltage on a node between the first diode and the first resistor and a voltage on a node between the second resistor and the third resistor for comparative amplification. A transistor is connected between the output terminal and a second reference voltage and having a control terminal to receive an output from the first comparator.

摘要翻译： 参考电压发生器电路包括第一电流路径和第二电流路径。 第一电流路径形成在提供有第一参考电压的输入端子和输出端子之间，并且包括第一二极管和从输入端子串联连接的第一电阻器。 第二电流路径形成在输入端子和输出端子之间，并且包括从输入端子串联连接的第二二极管，第二电阻器和第三电阻器。 比较器在第一二极管和第一电阻之间的节点上提供电压，并且在第二电阻器和第三电阻器之间的节点上的电压用于比较放大。 晶体管连接在输出端和第二参考电压之间，并且具有用于接收来自第一比较器的输出的控制端。

公开(公告)号：US07583114B2

公开(公告)日：2009-09-01

申请号：US11684214

申请日：2007-03-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G01R19/16552 ,  G01R19/16519 ,  G11C5/147

摘要： A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

摘要翻译： 电源电压检测电路包括内部电源电路，其提供恒定的输出电压，而不管电源电压如何。 延迟电路通过延迟输出电压的变化来产生延迟信号。 分压电路通过以一定的分频比除电源电压来产生分压。 p型MOS晶体管具有给定延迟信号的源极和给定分压的栅极，并且当电源电压降低到一定值以下时导通。 输出电路基于p型MOS晶体管上的漏极电压提供输出电压。

公开(公告)号：US07443709B2

公开(公告)日：2008-10-28

申请号：US11599363

申请日：2006-11-15

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C29/02 ,  G11C5/147 ,  G11C7/04 ,  G11C7/062 ,  G11C7/14 ,  G11C11/22 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/065

摘要： A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.

摘要翻译： 第一位线连接到存储器单元。 第二位线连接到具有虚拟电容器的虚拟单元，并且提供与第一位线的电位互补的电位。 读出放大器比较和放大第一和第二位线。 读出放大器电源电压产生电路为读出放大器提供读出放大器电源电压，以便由读出放大器进行比较和放大。 读出放大器电源电压被提供给参考电位产生电路。 当数据从存储单元读出到第一位线时，参考电位产生电路经由虚拟单元向第二位线提供与读出放大器电源电压的波动成正相关的波动的基准电位。