公开(公告)号：US07602017B2

公开(公告)日：2009-10-13

申请号：US11685364

申请日：2007-03-13

申请人： Jun Cai

发明人： Jun Cai

IPC分类号： H01L29/36

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7834

摘要： Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

摘要翻译： 低压，中压和高电压CMOS器件具有与源极和漏极和栅极延伸但不超过栅极中间的源极和漏极相同的导电类型的上缓冲层，以及较低的主缓冲层 与上缓冲层相反的导电类型从上缓冲层下延伸到栅极的中间，形成门下的两个体缓冲层的重叠。 可以使用两个掩模层为NMOS和PMOS FET注入上缓冲层和下块体缓冲层。 对于中压和高电压器件，上部缓冲层与较低的主缓冲层一起提供了一个复原区域。

公开(公告)号：US20080292918A1

公开(公告)日：2008-11-27

申请号：US11807190

申请日：2007-05-25

申请人： Caine Finnerty ,  Yanhai Du ,  Jun Cai

发明人： Caine Finnerty ,  Yanhai Du ,  Jun Cai

IPC分类号： H01M8/04 ,  H01M4/00 ,  H01M8/10 ,  H01M8/00

CPC分类号： H01M8/04365 ,  C25B9/18 ,  C25B15/02 ,  H01M8/04559 ,  H01M8/04604 ,  H01M8/04619 ,  H01M8/083 ,  H01M8/086 ,  H01M8/1011 ,  H01M8/243 ,  H01M8/2435 ,  H01M2008/1095 ,  H01M2008/1293 ,  H01M2008/147 ,  Y02E60/523 ,  Y02E60/525 ,  Y02E60/526

摘要： The present teachings relate to an electrochemical system including an electrochemical device and multiple independent circuits which permit independent control of the reaction rates at different sections of the electrochemical device. The electrochemical device can be a fuel cell or an electrolyzer, and can include a common electrode in electrical communication with two or more independent circuits. The present teachings also relate to operating methods of the electrochemical system described.

摘要翻译： 本教导涉及包括电化学装置和允许独立控制电化学装置的不同部分处的反应速率的多个独立电路的电化学系统。 电化学装置可以是燃料电池或电解槽，并且可以包括与两个或多个独立电路电连通的公共电极。 本教导还涉及所描述的电化学系统的操作方法。

公开(公告)号：US20080224210A1

公开(公告)日：2008-09-18

申请号：US11685364

申请日：2007-03-13

申请人： Jun Cai

发明人： Jun Cai

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7834

摘要： Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

摘要翻译： 低压，中压和高电压CMOS器件具有与源极和漏极和栅极延伸但不超过栅极中间的源极和漏极相同的导电类型的上缓冲层，以及较低的主缓冲层 与上缓冲层相反的导电类型从上缓冲层下延伸到栅极的中间，形成门下的两个体缓冲层的重叠。 可以使用两个掩模层为NMOS和PMOS FET注入上缓冲层和下块体缓冲层。 对于中压和高电压器件，上部缓冲层与较低的主缓冲层一起提供了一个复原区域。

公开(公告)号：US20080164537A1

公开(公告)日：2008-07-10

申请号：US11619828

申请日：2007-01-04

申请人： Jun Cai

发明人： Jun Cai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7835

摘要： Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

摘要翻译： 互补RF LDMOS晶体管在分隔栅极氧化物上具有栅电极。 第二导电类型的源间隔物从第一导电类型的源极阱横向延伸到最薄栅极氧化物上方的栅电极的大约边缘。 第一导电类型的主体从源极抽头的大约底部中心延伸到衬底表面，并且位于分裂栅极氧化物的薄部分的大部分之下。 源间隔物大约是栅极侧壁氧化物的长度，并且与栅电极自对准。 身体也与门电极自对准。 漏极由至少一个缓冲区包围，该缓冲区与最厚栅极氧化物上方的栅极电极的另一边缘自对准，并延伸到漏极的下方，并在最厚栅极氧化物下方横向延伸。 源极漏极和漏极都与栅极侧壁氧化物自对准，从而与栅电极横向间隔开。

公开(公告)号：US20080048779A1

公开(公告)日：2008-02-28

申请号：US11872630

申请日：2007-10-15

申请人： Philip Crawley ,  Amit Gattani ,  Jun Cai

发明人： Philip Crawley ,  Amit Gattani ,  Jun Cai

IPC分类号： H04L25/00 ,  H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/26 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2200/114 ,  H03F2200/372 ,  H03F2200/541 ,  H03F2203/21145 ,  H03F2203/45082 ,  H03F2203/45084 ,  H03F2203/45212 ,  H04L25/0276

摘要： A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an active common mode suppression circuit coupled to the interface in parallel to differential signal lines of the electronic device.

摘要翻译： 网络设备包括将电子设备耦合到差分信号线对的接口以及与电子设备的差分信号线并联连接到接口的有源共模抑制电路。

公开(公告)号：US20070288255A1

公开(公告)日：2007-12-13

申请号：US11746066

申请日：2007-05-09

申请人： Jun Cai ,  Yi You

发明人： Jun Cai ,  Yi You

IPC分类号： G06Q10/00 ,  G06Q30/00 ,  G05B19/418

CPC分类号： G06Q10/06

摘要： A method for the assigning rack space in an Internet data center is disclosed. The method includes defining a fragment space from the rack space and defining a fragment space threshold. When a business requesting a rack space is received, a space from the fragment space is assigned to the business if it is determined that the size of space requested by the business is smaller than the fragment space threshold.

摘要翻译： 公开了一种在互联网数据中心中分配机架空间的方法。 该方法包括从机架空间定义分段空间并且定义分段空间阈值。 当接收到请求机架空间的业务时，如果确定业务请求的空间大小小于分段空间阈值，则从分段空间分配空间给业务。

公开(公告)号：US20070228463A1

公开(公告)日：2007-10-04

申请号：US11695199

申请日：2007-04-02

申请人： Jun Cai

发明人： Jun Cai

IPC分类号： H01L29/76

CPC分类号： H01L29/0869 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66689

摘要： The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low threshold voltage version with a thin gate oxide on the source side of the device and a high threshold voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA, to reduce the device size and to reduce the device leakage.

摘要翻译： 本发明包括具有减小尺寸，高击穿电压和低导通电阻的横向双扩散金属氧化物半导体（LDMOS）。 这通过在器件的漏极侧提供厚栅极氧化物来实现，其在关断状态下减少电场拥挤以降低击穿电压并在漂移区域中形成积聚层，以减少在线状态下的器件电阻， 州。 该器件的一个版本包括在器件的源极侧具有薄栅极氧化物的低阈值电压版本，器件的高阈值电压版本包括源极侧的厚栅极氧化物。 LDMOS可以被配置为具有N型源的LNDMOS或具有P型源的LPDMOS。 器件的源极完全对准在栅极附近的氧化物隔离物处，以提供大的SOA，以减少器件尺寸并减少器件泄漏。

公开(公告)号：US20050239253A1

公开(公告)日：2005-10-27

申请号：US11069900

申请日：2005-03-01

申请人： Jun Cai

发明人： Jun Cai

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

摘要： A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.

摘要翻译： 包括LDMOS器件结构的半导体集成电路包括在半导体层的上表面上的具有一对间隔开的场效应栅极结构的半导体层。 第一导电类型的第一和第二间隔开的源极区域形成在一对栅极结构之间的层的一部分中，其间形成有第二导电类型的第一区域。 在半导体层中形成第二导电类型的轻掺杂体区域，从源极区域的下方延伸到栅极结构的下方，并将可变深度延伸到半导体层中。 该身体区域的特征在于在第一区域的下方延伸的身体区域的部分中的深度变化。

公开(公告)号：US20050146954A1

公开(公告)日：2005-07-07

申请号：US10506274

申请日：2003-02-17

申请人： Naing Win ,  Jun Cai ,  Joseph Jimson ,  Weng Lam

发明人： Naing Win ,  Jun Cai ,  Joseph Jimson ,  Weng Lam

IPC分类号： G06F1/26 ,  G06F1/30 ,  G06F12/16 ,  G11C5/14 ,  G11C16/20 ,  G11C16/22 ,  G11C7/00

CPC分类号： G06F1/30 ,  G11C5/143 ,  G11C16/20 ,  G11C16/225

摘要： The product has a power supply (P2) and a processor (P). The processor (P) has an input (PDD) for receiving a power-down signal indicating a status of the power supply (P2) and another input (Q) connected to another supply. The product also has a non-volatile memory (M) for storing data supplied by the processor (P). The processor (P) has an algorithm to detect a power-down status of the power supply (P2) by repeatedly checking the power-down signal and, upon detection that the power-down signal has a value (S0) corresponding to the power-down status, to complete an ongoing writing operation and stop the storage of data. The method prevents incorrect storage of data in a non-volatile memory by using the mentioned algorithm.

摘要翻译： 该产品具有电源（P 2）和一个处理器（P）。 处理器（P）具有用于接收指示电源状态（P 2）的断电信号和与另一电源连接的另一输入（Q）的输入（PDD）。 该产品还具有用于存储由处理器（P）提供的数据的非易失性存储器（M）。 处理器（P）具有通过重复检查掉电信号来检测电源（P 2）的掉电状态的算法，并且在检测到掉电信号具有对应于 停电状态，完成持续写入操作并停止数据存储。 该方法通过使用上述算法防止数据在非易失性存储器中的不正确存储。

公开(公告)号：US20050093070A1

公开(公告)日：2005-05-05

申请号：US10978627

申请日：2004-11-01

申请人： Jun Cai ,  Keng Lo

发明人： Jun Cai ,  Keng Lo

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L31/062

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S257/90

摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

摘要翻译： 描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。 该器件通过在源极和漏极区域下方添加n阱来实现。 通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。 这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。 该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。