公开(公告)号：US06491042B1

公开(公告)日：2002-12-10

申请号：US09206745

申请日：1998-12-07

申请人： Bao-Ru Young ,  Chia-Shiung Tsai

发明人： Bao-Ru Young ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  B08B7/00

摘要： A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

摘要翻译： 三步聚合物去除方法，其反转除去聚合物的常规顺序。 在本发明的优选实施方案中，首先从气体沉积台中除去聚合物，然后从所形成的接触孔的内表面剥离聚合物。

公开(公告)号：US06457477B1

公开(公告)日：2002-10-01

申请号：US09624020

申请日：2000-07-24

申请人： Bao-Ru Young ,  Li-Chih Chao ,  Shwangming Jeng ,  Chi-Shiung Tsai

发明人： Bao-Ru Young ,  Li-Chih Chao ,  Shwangming Jeng ,  Chi-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/76807 ,  Y10S134/902 ,  Y10S438/906 ,  Y10S438/963

摘要： A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27° C., and more preferably about 25° C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H2He gas.

摘要翻译： 一种清洁低k材料蚀刻开口的方法，包括以下步骤。 提供其中具有暴露设备的半导体结构。 在半导体结构和暴露的器件上形成蚀刻停止层。 在蚀刻停止层半导体结构和器件上形成一层低k材料。 在低k材料层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层用作掩模以蚀刻低k材料层被蚀刻以形成暴露在该器件上的蚀刻停止层的至少一部分的开口。 通过低温灰化过程在约23至27℃，更优选约25℃（室温）的温度下除去图案化的光致抗蚀剂层。 去除器件上的蚀刻停止层的暴露部分，通过低压，低偏压蚀刻工艺在约8至12毫乇的压力和约25至35瓦的偏压功率下暴露下层器件。 通过使用H2He气体通过完全干式清洁方法除去任何剩余的低压，低偏压蚀刻聚合物和蚀刻残留物来清洁露出的下部器件和开口。

公开(公告)号：US5968278A

公开(公告)日：1999-10-19

申请号：US206744

申请日：1998-12-07

申请人： Bao-Ru Young ,  Chia-Shiung Tsai ,  Wen-Chuan Chiang

发明人： Bao-Ru Young ,  Chia-Shiung Tsai ,  Wen-Chuan Chiang

IPC分类号： H01L21/311 ,  H01L21/768 ,  B08B6/00

CPC分类号： H01L21/76816 ,  H01L21/31138

摘要： An improved etching procedure that uses three processing steps to vastly improve HAR opening profile and improved under-layer selectivity. A new three sequence etching process is provided during which a new three-gas plasma etch is to be used. This new etching sequence is preceded by a new main etch that uses three gasses and followed by a new over-etch procedure that uses the same three gasses and etching conditions as the new main etch.

摘要翻译： 改进的蚀刻步骤使用三个加工步骤大大改善HAR开口轮廓和改进的底层选择性。 提供了一种新的三序蚀刻工艺，其中将使用新的三气等离子体蚀刻。 这个新的蚀刻序列之前是一个新的主要蚀刻，使用三个气体，然后采用与新的主蚀刻相同的三个气体和蚀刻条件的新的过蚀刻程序。

公开(公告)号：US08003467B2

公开(公告)日：2011-08-23

申请号：US12433356

申请日：2009-04-30

申请人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US20110278646A1

公开(公告)日：2011-11-17

申请号：US13194332

申请日：2011-07-29

申请人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L27/092

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US20100109088A1

公开(公告)日：2010-05-06

申请号：US12433356

申请日：2009-04-30

申请人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L27/092 ,  H01L21/20 ,  H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US06860275B2

公开(公告)日：2005-03-01

申请号：US10290128

申请日：2002-11-07

申请人： Bao-Ru Young ,  Chia-Shiung Tsai

发明人： Bao-Ru Young ,  Chia-Shiung Tsai

IPC分类号： B08B7/00 ,  H01L21/02 ,  H01L21/302 ,  C23F5/00

CPC分类号： H01L21/02063 ,  B08B7/00

摘要： A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

摘要翻译： 三步聚合物去除方法，其反转除去聚合物的常规顺序。 在本发明的优选实施方案中，首先从气体沉积台中除去聚合物，然后从所形成的接触孔的内表面剥离聚合物。

公开(公告)号：US06620462B1

公开(公告)日：2003-09-16

申请号：US10154286

申请日：2002-05-23

申请人： Ya-Chien Huang ,  Bao-Ru Young ,  Shin-Shiung Chen

发明人： Ya-Chien Huang ,  Bao-Ru Young ,  Shin-Shiung Chen

IPC分类号： B05D136

CPC分类号： G02B1/14 ,  C03C17/3435 ,  C03C17/3482 ,  C03C2218/365 ,  G02B1/105

摘要： A new method is provided for the creation of a protective layer over a glass substrate, the glass substrate has a first and a second surface. Under a first embodiment of the invention, a second surface of the glass panel is first coated with a layer of TiN. A first layer of amorphous silicon (A—Si) is deposited over the second surface of the glass panel. A second layer of amorphous silicon (A—Si) is deposited over the layer of TiN. A layer of photoresist is next deposited over the surface of the second layer of A—Si. The first layer of A—Si is removed from the second surface of the glass panel after which the layer of photoresist is removed. Under a second embodiment of the invention, the first and the second surface of the glass panel are coated with a first and a second layer of TiN. A layer of amorphous silicon (A—Si) is deposited over the second layer of TiN. A layer of photoresist is deposited over the layer of A—Si. The first layer of TiN on the first surface of the glass panel is removed after which the layer of photoresist is removed.

摘要翻译： 提供了一种用于在玻璃基板上形成保护层的新方法，玻璃基板具有第一和第二表面。 在本发明的第一实施例中，玻璃面板的第二表面首先涂覆有一层TiN。 第一层非晶硅（A-Si）沉积在玻璃面板的第二表面上。 第二层非晶硅（A-Si）沉积在TiN层上。 接着在第二层A-Si的表面上沉积一层光致抗蚀剂。 从玻璃面板的第二表面去除第一层A-Si层，之后除去光致抗蚀剂层。 在本发明的第二实施例中，玻璃面板的第一和第二表面涂覆有第一和第二层TiN。 在第二层TiN上沉积一层非晶硅（A-Si）。 一层光致抗蚀剂沉积在A-Si层上。 除去玻璃板的第一表面上的第一TiN层，然后除去光致抗蚀剂层。

公开(公告)号：US09711415B2

公开(公告)日：2017-07-18

申请号：US13469645

申请日：2012-05-11

申请人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823857

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

公开(公告)号：US20130234254A1

公开(公告)日：2013-09-12

申请号：US13415967

申请日：2012-03-09

申请人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

摘要翻译： 公开了一种制造具有混合HK /金属栅极堆叠制造的半导体器件的工艺。 该方法包括提供在PFET区域和NFET区域之间具有多个隔离特征的半导体衬底，以及在半导体衬底上形成栅叠层。 在PFET区域中，栅极堆叠形成为HK /金属栅极。 在NFET区域中，栅堆叠形成为多晶硅栅极。 通过利用另一个多晶硅栅极也在半导体衬底上形成高电阻。