公开(公告)号：US06620462B1

公开(公告)日：2003-09-16

申请号：US10154286

申请日：2002-05-23

申请人： Ya-Chien Huang ,  Bao-Ru Young ,  Shin-Shiung Chen

发明人： Ya-Chien Huang ,  Bao-Ru Young ,  Shin-Shiung Chen

IPC分类号： B05D136

CPC分类号： G02B1/14 ,  C03C17/3435 ,  C03C17/3482 ,  C03C2218/365 ,  G02B1/105

摘要： A new method is provided for the creation of a protective layer over a glass substrate, the glass substrate has a first and a second surface. Under a first embodiment of the invention, a second surface of the glass panel is first coated with a layer of TiN. A first layer of amorphous silicon (A—Si) is deposited over the second surface of the glass panel. A second layer of amorphous silicon (A—Si) is deposited over the layer of TiN. A layer of photoresist is next deposited over the surface of the second layer of A—Si. The first layer of A—Si is removed from the second surface of the glass panel after which the layer of photoresist is removed. Under a second embodiment of the invention, the first and the second surface of the glass panel are coated with a first and a second layer of TiN. A layer of amorphous silicon (A—Si) is deposited over the second layer of TiN. A layer of photoresist is deposited over the layer of A—Si. The first layer of TiN on the first surface of the glass panel is removed after which the layer of photoresist is removed.

摘要翻译： 提供了一种用于在玻璃基板上形成保护层的新方法，玻璃基板具有第一和第二表面。 在本发明的第一实施例中，玻璃面板的第二表面首先涂覆有一层TiN。 第一层非晶硅（A-Si）沉积在玻璃面板的第二表面上。 第二层非晶硅（A-Si）沉积在TiN层上。 接着在第二层A-Si的表面上沉积一层光致抗蚀剂。 从玻璃面板的第二表面去除第一层A-Si层，之后除去光致抗蚀剂层。 在本发明的第二实施例中，玻璃面板的第一和第二表面涂覆有第一和第二层TiN。 在第二层TiN上沉积一层非晶硅（A-Si）。 一层光致抗蚀剂沉积在A-Si层上。 除去玻璃板的第一表面上的第一TiN层，然后除去光致抗蚀剂层。

公开(公告)号：US09093559B2

公开(公告)日：2015-07-28

申请号：US13415967

申请日：2012-03-09

申请人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

摘要翻译： 公开了一种制造具有混合HK /金属栅极堆叠制造的半导体器件的工艺。 该方法包括提供在PFET区域和NFET区域之间具有多个隔离特征的半导体衬底，以及在半导体衬底上形成栅叠层。 在PFET区域中，栅极堆叠形成为HK /金属栅极。 在NFET区域中，栅堆叠形成为多晶硅栅极。 通过利用另一个多晶硅栅极也在半导体衬底上形成高电阻。

公开(公告)号：US20130299913A1

公开(公告)日：2013-11-14

申请号：US13469645

申请日：2012-05-11

申请人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/283

CPC分类号： H01L21/823842 ,  H01L21/823857

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US20130285151A1

公开(公告)日：2013-10-31

申请号：US13457079

申请日：2012-04-26

申请人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

公开(公告)号：US20130264652A1

公开(公告)日：2013-10-10

申请号：US13440848

申请日：2012-04-05

申请人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L27/092

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

公开(公告)号：US20130260547A1

公开(公告)日：2013-10-03

申请号：US13434344

申请日：2012-03-29

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

摘要翻译： 一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。 在栅介质层上形成三层元件。 三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。 使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。 第一覆盖层可以是用于图案化金属栅极层的牺牲层。

公开(公告)号：US08546227B2

公开(公告)日：2013-10-01

申请号：US13289112

申请日：2011-11-04

申请人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

发明人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

摘要翻译： 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。

公开(公告)号：US20130069174A1

公开(公告)日：2013-03-21

申请号：US13289112

申请日：2011-11-04

申请人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

发明人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

摘要翻译： 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。

公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US20130032884A1

公开(公告)日：2013-02-07

申请号：US13195628

申请日：2011-08-01

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/336

CPC分类号： H01L29/42376 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785 ,  H01L2223/58

摘要： A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2).

摘要翻译： 一种器件，以及制造和/或设计这种器件的方法，包括具有宽度（W）和长度（L）的第一栅极结构以及与第一栅极结构分离大于的距离的第二栅极结构： √{平方根（W * W + L * L）}）/ 10。 第二栅极结构是与第一栅极结构相邻的下一个栅极结构。 还描述了一种用于设计集成电路的方法和装置，包括实现限定栅极结构分离的设计规则。 在实施例中，对于相对于衬底上的其它栅极结构（例如，大于3μm2）较大的栅极结构，实现分离距离。