公开(公告)号：US20110278646A1

公开(公告)日：2011-11-17

申请号：US13194332

申请日：2011-07-29

申请人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L27/092

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US20100109088A1

公开(公告)日：2010-05-06

申请号：US12433356

申请日：2009-04-30

申请人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L27/092 ,  H01L21/20 ,  H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US08003467B2

公开(公告)日：2011-08-23

申请号：US12433356

申请日：2009-04-30

申请人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

发明人： Jin-Aun Ng ,  Wen-Chih Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

摘要翻译： 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

申请人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08450161B2

公开(公告)日：2013-05-28

申请号：US13465551

申请日：2012-05-07

申请人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20100044803A1

公开(公告)日：2010-02-25

申请号：US12389535

申请日：2009-02-20

申请人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20100052072A1

公开(公告)日：2010-03-04

申请号：US12368044

申请日：2009-02-09

申请人： Chii-Horng Li ,  Po-Nien Chen ,  Chung-Hau Fei ,  Chien-Liang Chen ,  Wen-Chih Yang ,  Harry Chuang

发明人： Chii-Horng Li ,  Po-Nien Chen ,  Chung-Hau Fei ,  Chien-Liang Chen ,  Wen-Chih Yang ,  Harry Chuang

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0629

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成金属层， 金属层和覆盖层，在第一区域中的金属层上形成多晶硅层，并在第二区域中的高k电介质层上方形成多晶硅层，并在第一区域中形成具有金属层的有源器件，并形成 在第二区域中没有金属层的无源器件。

公开(公告)号：US08889501B2

公开(公告)日：2014-11-18

申请号：US13486240

申请日：2012-06-01

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/11

CPC分类号： H01L27/1116 ,  H01L21/823807 ,  H01L21/823814

摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

摘要翻译： 一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。 执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。 执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。 第二硅层与源极/漏极应力源重叠。

公开(公告)号：US09324622B2

公开(公告)日：2016-04-26

申请号：US13586472

申请日：2012-08-15

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成栅极叠层，在邻近栅极叠层的边缘的衬底中形成非晶化区域，在衬底上形成应力膜，执行用pinchoff形成位错的过程 在衬底中去除至少一部分位错以在衬底中形成具有尖端的凹腔，并且在凹腔中形成源/漏特征。

公开(公告)号：US20140048886A1

公开(公告)日：2014-02-20

申请号：US13586472

申请日：2012-08-15

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成栅极叠层，在邻近栅极叠层的边缘的衬底中形成非晶化区域，在衬底上形成应力膜，执行用pinchoff形成位错的工艺 在衬底中去除至少一部分位错以在衬底中形成具有尖端的凹腔，并且在凹腔中形成源/漏特征。