公开(公告)号：US08536712B2

公开(公告)日：2013-09-17

申请号：US13014093

申请日：2011-01-26

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/18 ,  H01L23/49811 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00

摘要： A memory device has a laminated chip package and a controller plate. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller plate. A plurality of opposing wiring electrodes are formed at an opposing surface of the controller plate. A plurality of outside wiring electrodes are formed on the rear side of the opposing surface. Connection electrodes connecting the opposing wiring electrodes and the outside wiring electrodes are formed on the side surface of the controller plate. The interposed chip has a plurality of interposed wiring electrodes. The plurality of interposed wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of the plurality of opposing wiring electrodes. The controller plate is laid on the interposed chip.

摘要翻译： 存储器件具有层压芯片封装和控制器板。 在层叠芯片封装中，层叠多个存储芯片。 在层压芯片封装和控制板之间层压插入的芯片。 多个相对的布线电极形成在控制器板的相对表面处。 多个外部布线电极形成在相对表面的后侧。 连接相对的布线电极和外部布线电极的连接电极形成在控制器板的侧表面上。 插入的芯片具有多个插入的布线电极。 多个插入的布线电极形成有与多个相对的布线电极的配置图案相同的共同布置图案。 控制板放置在插入的芯片上。

公开(公告)号：US08525167B2

公开(公告)日：2013-09-03

申请号：US12588713

申请日：2009-10-26

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/522

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L23/585 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06551

摘要： In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates.

摘要翻译： 在层压芯片封装中，层叠多个半导体装置和与该半导体装置连接的配线电极的半导体板。 在层叠芯片封装的布线侧面，形成在半导体板的配线用侧面的内侧电极的端面。 层叠芯片封装还具有用于检查的内部电极的端面沿着半导体板的层叠方向连接用于检查的外部电极，仅对于半导体板中的两个相邻的半导体板。

公开(公告)号：US08498077B1

公开(公告)日：2013-07-30

申请号：US13556654

申请日：2012-07-24

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Shigeki Tanemura ,  Tatsuya Shimizu

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Shigeki Tanemura ,  Tatsuya Shimizu

IPC分类号： G11B5/147

CPC分类号： G11B5/1278 ,  G11B5/17 ,  G11B5/3116 ,  G11B5/3123 ,  G11B5/3146 ,  G11B5/315

摘要： A magnetic head includes first to third coils, a main pole, a write shield, first and second yoke layers, and first and second coupling parts. The first and second yoke layers are magnetically connected to the write shield. The first yoke layer is located on the leading side relative to the main pole, whereas the second yoke layer is located on the trailing side relative to the main pole. The first coupling part magnetically couples the main pole and the second yoke layer to each other. The second coupling part magnetically couples the first yoke layer and the second yoke layer to each other. The first coil is wound around the first coupling part, whereas the second and third coils are wound around the second coupling part.

摘要翻译： 磁头包括第一至第三线圈，主极，写入屏蔽，第一和第二磁轭层以及第一和第二耦合部分。 第一和第二磁轭层磁性连接到写入屏蔽。 第一磁轭层相对于主极位于前导侧，而第二磁轭层相对于主极位于后侧。 第一耦合部分将主极和第二磁轭层磁耦合到彼此。 第二耦合部分将第一磁轭层和第二磁轭层磁耦合到彼此。 第一线圈缠绕在第一耦合部分上，而第二线圈和第三线圈围绕第二耦合部分缠绕。

公开(公告)号：US08493687B2

公开(公告)日：2013-07-23

申请号：US12964313

申请日：2010-12-09

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/127

CPC分类号： G11B5/3163 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/315

摘要： A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section includes a yoke layer, and first and second coupling layers that magnetically couple the bottom shield and the yoke layer to each other. The first coupling layer is magnetically connected to the bottom shield. The second coupling layer magnetically couples the first coupling layer to the yoke layer. No end faces of the second coupling layer are exposed in the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other.

摘要翻译： 磁头包括屏蔽，以及第一和第二返回路径部分。 屏蔽件具有位于面向介质的表面中以围绕主极端面的端面。 屏蔽包括底部屏蔽，两个侧面屏蔽和顶部屏蔽。 第一返回路径部分包括轭层，以及使底屏蔽和轭层彼此磁耦合的第一和第二耦合层。 第一耦合层磁性地连接到底部屏蔽。 第二耦合层将第一耦合层磁耦合到轭层。 没有第二耦合层的端面在面向介质的表面中露出。 第二返回路径部分将顶部屏蔽和主极彼此磁耦合。

公开(公告)号：US08482105B2

公开(公告)日：2013-07-09

申请号：US12656458

申请日：2010-01-29

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/50 ,  H01L21/768 ,  H01L23/28 ,  H01L23/498 ,  H01L2224/16145

摘要： A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

摘要翻译： 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与所述多个沟槽部分中的至少任一个接触的单位区域; 以及布线电极，其部分布置在单元区域内。 此外，多个槽部具有宽口结构，其宽度在宽度方面比包括底部的槽下部宽的部分形成在其入口处。

公开(公告)号：US08462482B2

公开(公告)日：2013-06-11

申请号：US12363188

申请日：2009-01-30

申请人： Yoshitaka Sasaki ,  Atsushi Iijima ,  Hiroshi Ikejima

发明人： Yoshitaka Sasaki ,  Atsushi Iijima ,  Hiroshi Ikejima

IPC分类号： H01G4/06

CPC分类号： H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  Y10T29/435

摘要： In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

摘要翻译： 在根据本发明的陶瓷电容器中，在基板上垂直于基板的表面布置有叉指对的内部电极，并且将陶瓷电介质部件填充到该一对内部电极之间的间隙中。 因此，在形成陶瓷电介质部件之前和/或之后，内部电极的尺寸基本上不会发生变化，从而可以保持在内部电极时形成的尺寸。 根据该陶瓷电容器，由于可以容易地控制内部电极尺寸，因此也可以容易地进行内部电极间隔的尺寸控制。

公开(公告)号：US08461050B2

公开(公告)日：2013-06-11

申请号：US13157938

申请日：2011-06-10

申请人： Hironori Araki ,  Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Shigeki Tanemura ,  Yukinori Ikegawa

发明人： Hironori Araki ,  Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Shigeki Tanemura ,  Yukinori Ikegawa

IPC分类号： H01L21/311

CPC分类号： G11B5/314 ,  G11B5/3163 ,  G11B2005/0021 ,  H01L21/31116

摘要： A method of taper-etching a layer to be etched that is made of SiO2 or SiON and has a top surface. The method includes the step of forming an etching mask with an opening on the top surface of the layer to be etched, and the step of taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces that intersect at a predetermined angle is formed in the layer to be etched. The etching mask is formed of a material containing elemental Al. The step of taper-etching employs an etching gas that contains a main component gas, which contributes to the etching of the layer to be etched, and N2.

摘要翻译： 一种由SiO 2或SiON制成并具有顶表面的蚀刻层的蚀刻方法。 该方法包括以下步骤：在待蚀刻层的顶表面上形成具有开口的蚀刻掩模;以及将待蚀刻层的一部分从开口暴露的部分，通过反应 离子蚀刻，使得在被蚀刻层中形成具有以预定角度相交的两个壁面的凹槽。 蚀刻掩模由含有元素Al的材料形成。 锥蚀刻的步骤使用包含有助于蚀刻蚀刻层的主要成分气体和N 2的蚀刻气体。

公开(公告)号：US08454848B2

公开(公告)日：2013-06-04

申请号：US13235856

申请日：2011-09-19

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Hironori Araki ,  Kazuki Sato ,  Kazumasa Yasuda

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Hironori Araki ,  Kazuki Sato ,  Kazumasa Yasuda

IPC分类号： B29D11/00

CPC分类号： G11B5/314 ,  G11B5/3163 ,  G11B5/6088 ,  G11B2005/0021

摘要： A method of manufacturing the plasmon generator includes the steps of: forming a base part made of a dielectric material; forming a metal film that is to later become the plasmon generator; and forming a filler layer made of a dielectric material. The base part includes a base surface and a protruding part that protrudes from the base surface. The protruding part has a top surface that is different in level from the base surface, and a first sidewall connecting the top surface of the protruding part to the base surface. The metal film includes an adhesion part adhering to the first sidewall. The filler layer has a second sidewall disposed such that the adhesion part is interposed between the first sidewall and the second sidewall.

摘要翻译： 制造等离子体发生器的方法包括以下步骤：形成由电介质材料制成的基部; 形成以后成为等离子体发生器的金属膜; 并形成由介电材料制成的填充层。 基部包括基部表面和从基部表面突出的突出部分。 突出部分具有与基部表面不同的顶表面，以及将突出部分的顶表面连接到基部表面的第一侧壁。 金属膜包括附着在第一侧壁上的粘合部。 填料层具有第二侧壁，该第二侧壁设置成使得粘合部分插入在第一侧壁和第二侧壁之间。

公开(公告)号：US20130088066A1

公开(公告)日：2013-04-11

申请号：US13648155

申请日：2012-10-09

申请人： Yoshitaka Sasaki ,  Yusuke Ohkawara ,  Hiroaki Inaba

发明人： Yoshitaka Sasaki ,  Yusuke Ohkawara ,  Hiroaki Inaba

IPC分类号： B60N2/44

CPC分类号： B60N2/16 ,  B60N2/06 ,  B60N2/6009

摘要： A vehicle seat including: a moving member that moves as one with a rail configured to move in a vehicle front-rear direction; a seat cushion that is coupled to the moving member through a lifter mechanism, is disposed above the rail, and is configured such that the top-bottom direction position of the seat cushion is capable of being adjusted by the lifter mechanism; and a gap concealing member that extends between a vehicle rear direction lower portion of the seat cushion and the rail to conceal a gap between the seat cushion and the rail. The gap concealing member is integrally formed from the top end portion to the bottom end portion.

摘要翻译： 一种车辆座椅，包括：移动构件，其沿着车辆前后方向移动的轨道移动; 通过升降机构联接到移动构件的座垫被设置在轨道上方，并且构造成使得座垫的上下方向位置能够由升降机构调节; 以及间隙隐蔽构件，其在所述座垫的车辆后方下部与所述轨道之间延伸，以隐藏所述座垫与所述轨道之间的间隙。 间隙隐蔽构件从顶端部到底端部一体地形成。

公开(公告)号：US08415793B2

公开(公告)日：2013-04-09

申请号：US12929385

申请日：2011-01-20

申请人： Yoshitaka Sasaki ,  Tatsushi Shimizu

发明人： Yoshitaka Sasaki ,  Tatsushi Shimizu

IPC分类号： H01L23/50

CPC分类号： H01L23/49805 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.

摘要翻译： 用于电子部件封装的晶片用于制造多个电子部件封装，所述多个电子部件封装中的每一个包括：包含多个外部连接端子的基座; 以及至少一个电子部件芯片，其结合到所述基座并电连接到所述多个外部连接端子。 晶片具有多个对应于多个电子部件封装的外部连接端子组，用于保持多组外部连接端子的保持器和用于将多组外部连接端子彼此连接的联接部 。 晶片包括多个预基部，每个前基部将各自经受至少一个电子部件芯片的接合，并且将稍后彼此分离，从而它们将因此变为基部。