公开(公告)号：US08912042B2

公开(公告)日：2014-12-16

申请号：US13621540

申请日：2012-09-17

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L21/44

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/03 ,  H01L2224/83

摘要： In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

摘要翻译： 在层叠芯片封装的制造方法中，使用具有与其连接的至少一个附加封装的分层子结构来制造多个分层芯片封装。 分层子结构包括稍后要彼此分离的多个主体。 每个主体包括：具有顶表面和底表面并且包括彼此堆叠的多个层部分的主要部分; 以及设置在主要部件的顶表面和底表面中的至少一个上的多个主端子。 附加封装包括附加的半导体芯片和至少一个额外的端子，其电连接到附加的半导体芯片并与多个主端子中的至少一个接触。

公开(公告)号：US08867169B2

公开(公告)日：2014-10-21

申请号：US13473159

申请日：2012-05-16

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Yukinori Ikegawa ,  Atsushi Iijima ,  Tatsuya Shimizu

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Yukinori Ikegawa ,  Atsushi Iijima ,  Tatsuya Shimizu

IPC分类号： G11B5/127 ,  G11B5/147

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3123 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region.

摘要翻译： 磁头包括结合有写入屏蔽的磁性结构。 磁结构形成为包括第一磁性层，堆叠在第一磁性层上的第二磁性层和种子层。 第一磁性层具有位于介质相对表面中的前端面和顶面。 第二磁性层具有位于介质面向表面中的前端面和底面。 第一磁性层的顶表面包括第一区域和第二区域，第一区域包括位于介质面向表面中的端部以及比介质面向表面比第一区域更远的第二区域。 种子层不存在于第一磁性层的顶表面的第一区域上，但存在于第二区域上。

公开(公告)号：US08576514B2

公开(公告)日：2013-11-05

申请号：US13328431

申请日：2011-12-16

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/127

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/3123 ,  G11B5/3133 ,  G11B5/3136 ,  G11B5/315 ,  G11B5/607

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. The shield magnetic layer has a leading shield part. The leading shield part is disposed on a substrate side of the main magnetic pole layer. The leading shield part has a variable distance structure in which a rearmost part most distanced from the medium-opposing surface is distanced more from the main magnetic pole layer than is a foremost part on the main magnetic pole layer side.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 薄膜磁头具有屏蔽磁性层。 屏蔽磁性层具有前导屏蔽部分。 前导屏蔽部分设置在主磁极层的基板侧。 前导屏蔽部分具有可变的距离结构，其中最远离介质相对表面的最远部分比主磁极层侧的最前部更远离主磁极层。

公开(公告)号：US08552534B2

公开(公告)日：2013-10-08

申请号：US13286728

申请日：2011-11-01

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： H01L23/544 ,  H01L23/34

CPC分类号： H01L25/0657 ,  H01L22/32 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有多个器件区域，其中形成有彼此绝缘的半导体器件，以及多个布线电极，其连接到分别形成在多个器件区域中并从器件区域延伸的半导体器件 进入划痕槽部分的内部。 多个布线电极以局部布置图案布置，其中布线电极仅沿着四个边界侧的一部分布置，对应于每个装置区域和划线槽部分之间的边界。 此外，多个布线电极仅从彼此相邻的两个器件区域中的一个延伸到划线槽部分中，其间具有划线槽部分。

公开(公告)号：US08466562B2

公开(公告)日：2013-06-18

申请号：US12585778

申请日：2009-09-24

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/48

CPC分类号： H01L24/94 ,  H01L23/481 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2224/05552

摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.

摘要翻译： 分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。 多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。 半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。 在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。 第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。

公开(公告)号：US08441112B2

公开(公告)日：2013-05-14

申请号：US12896283

申请日：2010-10-01

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L25/50 ,  H01L22/22 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014

摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 第一和第二端子通过使用第一和第二层部分的电极形成。 层叠芯片封装通过层叠两个子结构（其中包括多个预备层部分的阵列），然后切割层状子结构而制造层状子结构来制造。 分层子结构包括多个初级线，其布置在两个相邻的预分离主体之间并且将成为多根线。

公开(公告)号：US08426981B2

公开(公告)日：2013-04-23

申请号：US13240048

申请日：2011-09-22

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

摘要： A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

摘要翻译： 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。

公开(公告)号：US20130057987A1

公开(公告)日：2013-03-07

申请号：US13224954

申请日：2011-09-02

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/31 ,  H04R31/00 ,  G11B5/33 ,  G11B5/48 ,  G11B5/187

CPC分类号： G11B5/1278 ,  G11B5/3106 ,  G11B5/3116 ,  G11B5/3136 ,  G11B5/607 ,  Y10T29/49032 ,  Y10T428/1186

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a leading shield part opposing the main magnetic pole layer on the substrate side of the main magnetic pole layer. The thin-film magnetic head has a substrate side coil layer disposed between the main magnetic pole layer and the substrate. In the thin-film magnetic head, a space between a lower end face of the leading shield part and the substrate and a space between an upper end face in the substrate side coil layer and the substrate are formed equal to each other.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 薄膜磁头具有与主磁极层的基板侧的主磁极层相对的主屏蔽部。 薄膜磁头具有设置在主磁极层和基板之间的基板侧线圈层。 在薄膜磁头中，形成前导屏蔽部的下端面与基板之间的空间与基板侧线圈层的上端面与基板之间的空间。

公开(公告)号：US08358015B2

公开(公告)日：2013-01-22

申请号：US13156941

申请日：2011-06-09

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。

公开(公告)号：US08310787B1

公开(公告)日：2012-11-13

申请号：US13246153

申请日：2011-09-27

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/31

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3163

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. The shield magnetic layer is connected to the main magnetic pole layer. The shield magnetic layer has a lower front shield part. A front end angle representing an angle formed between a front end face of the lower front shield part and a lower end face is set at an obtuse angle. The front end face is disposed in the medium-opposing surface. The lower end face is disposed at a position closest to the substrate in the lower front shield part.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 薄膜磁头具有屏蔽磁性层。 屏蔽磁性层连接到主磁极层。 屏蔽磁性层具有下部前屏蔽部分。 形成在下侧前屏蔽部的前端面与下端面之间的角度的前端角被设定为钝角。 前端面设置在介质相对面上。 下端面设置在下侧前屏蔽部的最靠近基板的位置。