公开(公告)号：US20090199190A1

公开(公告)日：2009-08-06

申请号：US12024389

申请日：2008-02-01

申请人： Lei Chen ,  Lixin Zhang

发明人： Lei Chen ,  Lixin Zhang

IPC分类号： G06F9/46

CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/1016

摘要： A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.

摘要翻译： 一种用于实现基于优先级调度和限制预取操作的框架的方法，处理器和数据处理系统。 预取引擎（PE）将优先级分配给第一预取流，指示用于调度第一预取流的预取操作的相对优先级。 PE监视数据处理系统内的活动，并基于活动（或缺乏）动态地更新第一预取流的优先级。 低优先级流可能被丢弃。 PE还在基于优先级的调度序列中调度预取，该调度序列对应于当前分配给调度的活动流的优先级。 当预取队列中没有预取时，PE触发活动流以提供预取。 根据与完成预取相关的资源的当前使用水平，PE确定何时限制预取。

公开(公告)号：US20090198907A1

公开(公告)日：2009-08-06

申请号：US12024411

申请日：2008-02-01

申请人： William E. Speight ,  Lixin Zhang

发明人： William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/1041 ,  G06F2212/6024

摘要： A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem. The first prefetch stream has a first assigned priority that determines a relative order for scheduling prefetch requests of the first prefetch stream relative to other prefetch requests of other prefetch streams. Based on the receipt of a processor demand for the data before the data returns to the cache or return of the data along time before the receiving the processor demand, logic of the prefetch engine dynamically changes the first assigned priority to a second higher or lower priority, which priority is subsequently utilized to schedule and issue a next prefetch request of the first prefetch stream.

摘要翻译： 一种用于基于处理器的数据的消耗速率动态地调整预取流优先级的方法，处理器和数据处理系统。 该方法包括预取引擎，其发出第一预取流的预取请求以从存储器子系统获取一个或多个数据。 第一预取流具有第一分配的优先级，其相对于其他预取流的其他预取请求确定第一预取流的调度预取请求的相对顺序。 基于在数据返回到高速缓存之前对数据的接收处理器需求，或者在接收到处理器需求之前的时间返回数据，预取引擎的逻辑动态地将第一分配的优先级改变为第二较高或更低的优先级 随后利用该优先级来调度和发出第一预取流的下一个预取请求。

公开(公告)号：US20090198903A1

公开(公告)日：2009-08-06

申请号：US12024170

申请日：2008-02-01

申请人： RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

发明人： RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0822 ,  G06F2212/507 ,  G06F2212/6028

摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.

摘要翻译： 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

公开(公告)号：US20090077354A1

公开(公告)日：2009-03-19

申请号：US11856170

申请日：2007-09-17

申请人： Ram Rangan ,  William E. Speight ,  Mark W. Stephenson ,  Lixin Zhang

发明人： Ram Rangan ,  William E. Speight ,  Mark W. Stephenson ,  Lixin Zhang

IPC分类号： G06F9/318

CPC分类号： G06F9/3851 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/384

摘要： A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.

摘要翻译： 用于处理无序处理器中的预定代码的技术包括检测与预定代码区相关联的谓词定义指令。 然后，在预定的代码区域内重命名预定的指令，直到谓词定义指令的谓词解决为止。

公开(公告)号：US20090049286A1

公开(公告)日：2009-02-19

申请号：US11837893

申请日：2007-08-13

申请人： David S. Levitan ,  William E. Speight ,  Lixin Zhang

发明人： David S. Levitan ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.

摘要翻译： 处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。 指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。 分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。 分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址 以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。

公开(公告)号：US07464115B2

公开(公告)日：2008-12-09

申请号：US11113805

申请日：2005-04-25

申请人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

发明人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

IPC分类号： G06F13/42

CPC分类号： G06F15/16 ,  Y10S707/99952

摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

摘要翻译： 用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到 在确定每个节点已访问存储器之后，节点集合。 完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

公开(公告)号：US20080114136A1

公开(公告)日：2008-05-15

申请号：US11795571

申请日：2006-01-23

申请人： Toshiaki Suzuki ,  Lixin Zhang ,  Zhaomin Hou

发明人： Toshiaki Suzuki ,  Lixin Zhang ,  Zhaomin Hou

IPC分类号： C08F4/06 ,  C07F5/00

CPC分类号： C07F9/5045 ,  C07F5/00 ,  C07F7/0803 ,  C08F4/54 ,  C08F36/04 ,  C08F36/06 ,  C08F4/545

摘要： The present invention provides 1) a complex comprising a mono-anionictridentate ligand, represented by the following general formula (I); 2) a polymerization catalyst composition, comprising the complex; and 3) a cis-1,4-isoprene polymer, a cis-1,4-butadiene polymer, a cis-1,4-isoprene-styrene copolymer, a cis-1,4-butadiene-styrene copolymer, a cis-1,4-butadiene-cis-1,4-isoprene copolymer, and a cis-1,4-butadiene-cis-1,4-isoprene-styrene copolymer, each of which has high-cis-1,4 content in a micro structure and a sharp molecular-weight distribution.

摘要翻译： 本发明提供1）由以下通式（I）表示的单阴离子三配位配位体： 2）包含所述络合物的聚合催化剂组合物; 顺式-1,4-异戊二烯聚合物，顺式-1,4-丁二烯聚合物，顺式-1,4-异戊二烯 - 苯乙烯共聚物，顺式-1,4-丁二烯 - 苯乙烯共聚物，顺式-1,4-丁二烯 - 苯乙烯共聚物， 1,4-丁二烯 - 顺式-1,4-异戊二烯共聚物，顺式-1,4-丁二烯 - 顺式-1,4-异戊二烯 - 苯乙烯共聚物，其中， 微结构和尖锐的分子量分布。

公开(公告)号：US20070283101A1

公开(公告)日：2007-12-06

申请号：US11422459

申请日：2006-06-06

申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.

摘要翻译： 一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。 该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求） 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

公开(公告)号：US07281092B2

公开(公告)日：2007-10-09

申请号：US11143328

申请日：2005-06-02

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0817 ,  G06F12/0822

摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.

摘要翻译： 一种使用自适应机制管理缓存层次结构的系统和方法。 本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据 块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。 此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块 内存缓存被驱逐。

公开(公告)号：US10188657B2

公开(公告)日：2019-01-29

申请号：US15808223

申请日：2017-11-09

申请人： Lixin Zhang

发明人： Lixin Zhang

IPC分类号： A61K31/53

摘要： Provided are articles of manufacture, compositions and methods for prophylaxis and/or therapy for disorders involving dizziness and/or vertigo. The articles of manufacture and compositions contain lamotrigen and/or bupropion. The compositions include pharmaceutical compositions which are intended to alleviate dizziness and/or vertigo. In certain aspects the disclosure includes articles of manufacture and kits which include printed material which provides an indication that the articles or compositions are intended to be used for prophylaxis and/or therapy of Meniere's Disease or a symptom thereof.