公开(公告)号：US08569168B2

公开(公告)日：2013-10-29

申请号：US13371493

申请日：2012-02-13

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

摘要翻译： 形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

公开(公告)号：US20130221527A1

公开(公告)日：2013-08-29

申请号：US13404875

申请日：2012-02-24

申请人： Chih-Chao Yang ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Chao-Kun Hu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53223 ,  H01L21/76849 ,  H01L21/76882 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.

摘要翻译： 使用金属回流工艺来提供包括覆盖下面的导电金属特征的整个表面的80-99％的金属盖的互连结构。 导电金属特征的横向延伸部分位于金属盖的垂直边缘上，并且导电金属特征的每个横向延伸部分具有与金属盖的最上表面共面的最上表面。

公开(公告)号：US08492871B2

公开(公告)日：2013-07-23

申请号：US12268541

申请日：2008-11-11

申请人： Chih-Chao Yang ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L23/62

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

公开(公告)号：US08476160B2

公开(公告)日：2013-07-02

申请号：US12913116

申请日：2010-10-27

申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/02126 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

摘要翻译： 第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。 沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。 选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。 亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和 随后在互连级介电材料层中形成线沟槽。

公开(公告)号：US20130113101A1

公开(公告)日：2013-05-09

申请号：US13290577

申请日：2011-11-07

申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.

摘要翻译： 使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。 在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。 在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。 在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。 在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

公开(公告)号：US08420537B2

公开(公告)日：2013-04-16

申请号：US12127878

申请日：2008-05-28

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/76877 ,  H01L21/76883

摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。

公开(公告)号：US08405215B2

公开(公告)日：2013-03-26

申请号：US12906580

申请日：2010-10-18

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L23/52

CPC分类号： H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76835 ,  H01L21/76843

摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.

摘要翻译： 提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触 通过锚定区域。 此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。 因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。 还提供了一种形成这种互连结构的方法。

公开(公告)号：US20130043591A1

公开(公告)日：2013-02-21

申请号：US13211722

申请日：2011-08-17

申请人： Chih-Chao Yang ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Daniel C. Edelstein

IPC分类号： H01L23/482 ,  H01L21/283

CPC分类号： H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

公开(公告)号：US20130037865A1

公开(公告)日：2013-02-14

申请号：US13206586

申请日：2011-08-10

申请人： Takeshi Nogami ,  Keich Kwong Hon Wong ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Keich Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/28 ,  H01L29/78 ,  B82Y99/00

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/32056 ,  H01L29/66545

摘要： A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process.

摘要翻译： 一种半导体结构，其包括形成在半导体衬底上的沟槽或通孔中的半导体衬底和金属栅极结构。 金属栅极结构包括栅极电介质; 选自钴和镍的润湿层，位于沟槽或通孔上的栅极电介质上，氧含量不超过约200ppm（百万分之一）氧; 以及铝层以填补沟槽或通孔的其余部分。 还公开了一种形成半导体结构的方法，其中由通过化学气相沉积工艺沉积的脒化脒或脒化镍形成润湿层。

公开(公告)号：US20130005137A1

公开(公告)日：2013-01-03

申请号：US13609668

申请日：2012-09-11

申请人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

摘要翻译： 一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。 该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。 接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。 在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。 在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。