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公开(公告)号：US12183422B2
公开(公告)日：2024-12-31
申请号：US18166495
申请日：2023-02-09
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Feng-Min Lee , Tian-Cih Bo
Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.
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公开(公告)号：US12142316B2
公开(公告)日：2024-11-12
申请号：US17812783
申请日：2022-07-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee , Ming-Hsiu Lee
Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.
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公开(公告)号：US12114514B2
公开(公告)日：2024-10-08
申请号：US18519230
申请日：2023-11-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Erh-Kun Lai , Dai-Ying Lee , Yu-Hsuan Lin , Po-Hao Tseng , Ming-Hsiu Lee
CPC classification number: H10B63/845 , H10B61/22 , H10B63/34 , H10N50/01 , H10N70/066
Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
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54.发明授权公开(公告)号：US12068030B2
公开(公告)日：2024-08-20
申请号：US17524771
申请日：2021-11-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
CPC classification number: G11C15/046 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
Abstract: The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.
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公开(公告)号：US20240221830A1
公开(公告)日：2024-07-04
申请号：US18173096
申请日：2023-02-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Tian-Cih Bo , Feng-Min Lee
CPC classification number: G11C15/04 , G11C16/0483 , G11C16/26
Abstract: A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.
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Patent Agency Ranking
56.发明授权公开(公告)号：US11875849B2
公开(公告)日：2024-01-16
申请号：US17711073
申请日：2022-04-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng , Feng-Min Lee
IPC: G11C15/04
CPC classification number: G11C15/046
Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.
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公开(公告)号：US11748062B2
公开(公告)日：2023-09-05
申请号：US17344500
申请日：2021-06-10
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Feng-Min Lee , Yu-Hsuan Lin
CPC classification number: G06F7/523 , G06F7/02 , G06F7/50 , G06F7/5443 , G06F2207/4826
Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.
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公开(公告)号：US11657876B2
公开(公告)日：2023-05-23
申请号：US17325244
申请日：2021-05-20
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee
CPC classification number: G11C16/102 , G11C15/04 , G11C16/0433 , G11C16/26 , G11C16/3404
Abstract: An analog CAM and an operation method thereof are provided. The analog CAM includes a matching line, an analog CAM cell and a sense amplifier. Each of the at least one analog CAM includes a first floating gate device having a N type channel and a second floating gate device having a P type channel. A match range is set through programming the first floating gate device and the second floating gate device. The sense amplifier is connected to the matching line. If an inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level. The sense amplifier outputs a match result if the voltage of the matching line is pulled down to a predetermined level.
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公开(公告)号：US11328775B2
公开(公告)日：2022-05-10
申请号：US17065516
申请日：2020-10-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Ming-Hsiu Lee , Feng-Min Lee
Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.
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公开(公告)号：US20190156883A1
公开(公告)日：2019-05-23
申请号：US15817437
申请日：2017-11-20
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
Abstract: A neuromorphic computing device includes a plurality of row lines, a plurality of column lines and a plurality of synapses. The synapses are positioned at intersections of the row lines and column lines, respectively. The synapses include a first synapse and a second synapse. The first synapse includes a first resistance-adjustable element and a first transistor connected to the first resistance-adjustable element in series. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synapse includes a second resistance-adjustable element and a second transistor connected to the second resistance-adjustable element in series. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio differs from the second aspect ratio, and/or the first turn-on voltage differs from the second turn-on voltage.
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