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    TIMESTAMP CONTROL LOOP
    52.
    发明申请
    TIMESTAMP CONTROL LOOP 有权

    公开(公告)号：US20250047402A1

    公开(公告)日：2025-02-06

    申请号：US18229074

    申请日：2023-08-01

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Yam Gellis ,  Oren Matus ,  Liron Mula ,  Natan Manevich ,  Hillel Chapman ,  Dotan David Levi

    IPC: H04J3/06

    Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.

    Clock adjustment holdover
    53.
    发明授权
    Clock adjustment holdover 有权

    公开(公告)号：US12216489B2

    公开(公告)日：2025-02-04

    申请号：US18111916

    申请日：2023-02-21

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

    Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

    Clock Adjustment Holdover
    55.
    发明公开
    Clock Adjustment Holdover 审中-公开

    公开(公告)号：US20240281022A1

    公开(公告)日：2024-08-22

    申请号：US18111916

    申请日：2023-02-21

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

    IPC: G06F1/12 ,  G06F1/08

    CPC classification number: G06F1/12 ,  G06F1/08

    Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

    Work scheduling
    56.
    发明公开
    Work scheduling 审中-公开

    公开(公告)号：US20240168797A1

    公开(公告)日：2024-05-23

    申请号：US17988812

    申请日：2022-11-17

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Harsha Deepak Banuli Nanje Gowda ,  Natan Manevich ,  Daniel Marcovitch

    IPC: G06F9/48 ,  G06F1/12 ,  G06F13/40

    CPC classification number: G06F9/4881 ,  G06F1/12 ,  G06F13/405

    Abstract: In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.

    PRECISE MULTICAST TIMESTAMPING
    58.
    发明公开
    PRECISE MULTICAST TIMESTAMPING 审中-公开

    公开(公告)号：US20240089077A1

    公开(公告)日：2024-03-14

    申请号：US17942899

    申请日：2022-09-12

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

    IPC: H04L7/00 ,  H04L12/18

    CPC classification number: H04L7/0091 ,  H04L12/1881

    Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.

    Scalable synchronization of network devices
    59.
    发明授权
    Scalable synchronization of network devices 有权

    公开(公告)号：US11917045B2

    公开(公告)日：2024-02-27

    申请号：US17871937

    申请日：2022-07-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Arnon Sattinger ,  Natan Manevich ,  Wojciech Wasko ,  Ariel Almog ,  Bar Or Shapira

    IPC: H03L7/08 ,  G06F1/12 ,  H04L7/00

    CPC classification number: H04L7/0012

    Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.

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