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    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES
    51.
    发明申请
    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200212000A1

    公开(公告)日：2020-07-02

    申请号：US16236257

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

    Silicon interposer with fuse-selectable routing array
    52.
    发明授权
    Silicon interposer with fuse-selectable routing array 有权

    公开(公告)号：US10580720B1

    公开(公告)日：2020-03-03

    申请号：US16166428

    申请日：2018-10-22

    Applicant: Micron Technology, Inc.

    Inventor： Bret K. Street ,  Owen R. Fay ,  Eiichi Nakano

    IPC: H01L23/48 ,  H01L21/66 ,  H01L23/14 ,  H01L23/00 ,  H01L23/525 ,  H01L21/48 ,  H01L23/532

    Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.

    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
    54.
    发明授权
    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods 有权

    公开(公告)号：US10381329B1

    公开(公告)日：2019-08-13

    申请号：US15878755

    申请日：2018-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/48 ,  H01L25/00 ,  H01L23/64

    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
    57.
    发明授权
    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权

    公开(公告)号：US09786612B2

    公开(公告)日：2017-10-10

    申请号：US15446583

    申请日：2017-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/544

    CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
    58.
    发明授权
    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权
    处理晶圆级组件以减少翘曲的方法和相关组件

    公开(公告)号：US09589933B2

    公开(公告)日：2017-03-07

    申请号：US14312147

    申请日：2014-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC: H01L21/78 ,  H01L25/065

    CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES
    59.
    发明申请
    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES 有权
    加工水平组合减少威胁的方法和相关组织

    公开(公告)号：US20150371969A1

    公开(公告)日：2015-12-24

    申请号：US14312147

    申请日：2014-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC: H01L25/065 ,  H01L21/77

    CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

    STACKED SEMICONDUCTOR DEVICE
    60.
    发明申请
    STACKED SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250096202A1

    公开(公告)日：2025-03-20

    申请号：US18788541

    申请日：2024-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Wei Zhou

    IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

    Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

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