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Patent Agency Ranking
公开(公告)号：US20230266890A1
公开(公告)日：2023-08-24
申请号：US17677641
申请日：2022-02-22
Applicant: Micron Technology, Inc.
Inventor： Sriteja Yamparala , Fulvio Rori , Marco Domenico Tiburzi , Walter Di Francesco , Chiara Cerafogli , Tawalin Opastrakoon
CPC classification number: G06F3/0625 , G06F1/08 , G06F1/28 , G06F3/0653 , G06F3/0673
Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.
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公开(公告)号：US11626163B2
公开(公告)日：2023-04-11
申请号：US17464853
申请日：2021-09-02
Applicant: Micron Technology, Inc.
Inventor： Justin Bates , Giuseppe Cariello , Pitamber Shukla , Fulvio Rori , Chiara Cerafogli , Scott Anthony Stoller
Abstract: Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.
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公开(公告)号：US20230067570A1
公开(公告)日：2023-03-02
申请号：US17464853
申请日：2021-09-02
Applicant: Micron Technology, Inc.
Inventor： Justin Bates , Giuseppe Cariello , Pitamber Shukla , Fulvio Rori , Chiara Cerafogli , Scott Anthony Stoller
Abstract: Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.
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公开(公告)号：US20190180832A1
公开(公告)日：2019-06-13
申请号：US15835129
申请日：2017-12-07
Applicant: Micron Technology, Inc.
Inventor： Fulvio Rori , Chiara Cerafogli
Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.
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公开(公告)号：US08953379B2
公开(公告)日：2015-02-10
申请号：US14070911
申请日：2013-11-04
Applicant: Micron Technology, Inc.
Inventor： Chiara Cerafogli , Agostino Macerola
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/349
Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.
Abstract translation: 描述用于重新编程存储器单元的装置和方法。 用于存储器单元操作的一种或多种方法包括编程多个存储器单元，使得多个存储器单元中的每一个处于第一编程状态或第二编程状态，第二编程状态具有与其相关联的第一编程验证电压; 并且重新编程存储器单元的数量，使得多个存储器单元中的至少一个被重新编程到具有与其相关联的第二编程验证电压的第三编程状态，其中存储器单元的数量的阈值电压小于第二个 程序验证电压表示相同的数据值。
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