公开(公告)号：US11955158B2

公开(公告)日：2024-04-09

申请号：US18064773

申请日：2022-12-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/40 ,  G06F11/30 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076 ,  G11C16/34 ,  G11C7/00

CPC classification number: G11C11/40611 ,  G06F11/3037 ,  G11C7/1039 ,  G11C11/4076 ,  G11C16/3431 ,  G11C16/349 ,  G06F2201/88 ,  G11C7/00 ,  G11C2211/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US11755206B2

公开(公告)日：2023-09-12

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/161 ,  G11C8/00 ,  Y02D10/00

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US11264078B2

公开(公告)日：2022-03-01

申请号：US16781763

申请日：2020-02-04

Applicant: Micron Technology, inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C11/40 ,  G11C11/4076 ,  H03K19/20 ,  H03K3/037

Abstract: Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

公开(公告)号：US20210398592A1

公开(公告)日：2021-12-23

申请号：US17446710

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

公开(公告)号：US11158373B2

公开(公告)日：2021-10-26

申请号：US16437811

申请日：2019-06-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

公开(公告)号：US20210005240A1

公开(公告)日：2021-01-07

申请号：US16459520

申请日：2019-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C11/408

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US20200381040A1

公开(公告)日：2020-12-03

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US10832792B1

公开(公告)日：2020-11-10

申请号：US16459507

申请日：2019-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C7/00 ,  G11C29/00 ,  G11C11/408 ,  G11C11/406

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

公开(公告)号：US10685696B2

公开(公告)日：2020-06-16

申请号：US16176932

申请日：2018-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C7/00 ,  G11C11/406 ,  G11C16/34 ,  G11C7/10 ,  G06F11/30 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US10529409B2

公开(公告)日：2020-01-07

申请号：US15292941

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.