公开(公告)号：US12094531B2

公开(公告)日：2024-09-17

申请号：US17146314

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54

CPC classification number: G11C11/54 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US12061551B2

公开(公告)日：2024-08-13

申请号：US17896883

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0815

CPC classification number: G06F12/0815 ,  G06F2212/1032 ,  G06F2212/305

Abstract: An access counter associated with a segment of a memory device is maintained. An access notification for a first line of the segment is received. An access type associated with the access notification is identified. A first value of the access counter is changed by a second value based on the access type. Based on the first value of the access counter, a memory management scheme is implemented.

公开(公告)号：US12007899B2

公开(公告)日：2024-06-11

申请号：US17867371

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  David Andrew Roberts ,  Patrick Michael Sheridan ,  Lukasz Burzawa

IPC: G06F12/0882 ,  G06F12/06

CPC classification number: G06F12/0882 ,  G06F12/0646

Abstract: Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.

公开(公告)号：US20230393744A1

公开(公告)日：2023-12-07

申请号：US17831242

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Nabeel Meeramohideen Mohamed ,  Steven Andrew Moyer ,  David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for access heatmap implementations at a host device are described. A host device may leverage access operation monitoring that is performed at a memory device, including various examples of signaling and management of monitoring configurations. For example, a memory device may maintain a storage location for tracking access operation occurrence, for which access operations of a given address may be mapped to multiple fields, and for which each field may be associated with access operations of a respective subset of the addresses. In some examples, such registers may be configured or accessed based on indications (e.g., commands, requests) from a host device, which may support dynamic access operation monitoring that is responsive to various operating conditions. In some examples, the host device may perform evaluations based on such minimum values associated with respective addresses to determine a distribution of data across various portions of memory.

公开(公告)号：US11768770B2

公开(公告)日：2023-09-26

申请号：US17823480

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/0864 ,  G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F12/084 ,  G06F9/30047 ,  G06F9/30101 ,  G06F12/0284 ,  G06F12/0853 ,  G06F12/0864 ,  G06F13/1689 ,  G06F2212/1021

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US11693775B2

公开(公告)日：2023-07-04

申请号：US17657922

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/1044

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US20230061668A1

公开(公告)日：2023-03-02

申请号：US17823480

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0864

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US20230058668A1

公开(公告)日：2023-02-23

申请号：US17843571

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Tony M. Brewer

IPC: G06F12/14 ,  G06F12/0842

Abstract: A cache memory can maintain multiple cache lines and each cache line can include a data field, an encryption status attribute, and an encryption key attribute. The encryption status attribute can indicate whether the data field in the corresponding cache line includes encrypted or unencrypted data and the encryption key attribute can include an encryption key identifier for the corresponding cache line. In an example, a cryptographic controller can access keys from a key table to selectively encrypt or unencrypt cache data. Infrequently accessed cache data can be maintained as encrypted data, and more frequently accessed cache data can be maintained as unencrypted data. In some examples, different cache lines in the same cache memory can be maintained as encrypted or unencrypted data, and different cache lines can use respective different encryption keys.

公开(公告)号：US20230052043A1

公开(公告)日：2023-02-16

申请号：US17815516

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F12/0891

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.

公开(公告)号：US20220342568A1

公开(公告)日：2022-10-27

申请号：US17238791

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06 ,  G06F12/02

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.