公开(公告)号：US10789996B2

公开(公告)日：2020-09-29

申请号：US16360685

申请日：2019-03-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US20190384526A1

公开(公告)日：2019-12-19

申请号：US16555852

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US20190362759A1

公开(公告)日：2019-11-28

申请号：US16537775

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  G11C8/12 ,  H03K19/20 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/08

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20190341084A1

公开(公告)日：2019-11-07

申请号：US16514371

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/403 ,  G11C7/12 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US10418073B1

公开(公告)日：2019-09-17

申请号：US16163728

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Yu-Feng Chen

IPC: G05F1/10 ,  G11C5/14 ,  H02M3/07 ,  G11C16/30

Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The available charge pumps in a memory device may be adjusted through adjustment of the operation frequency of oscillating circuitry that drives the charge pump. Delay elements may also be adjusted to facilitate operation of the charge pump.

公开(公告)号：US20190206476A1

公开(公告)日：2019-07-04

申请号：US16193825

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C11/4074 ,  G06F11/10 ,  G11C29/52 ,  G11C11/4096

CPC classification number: G11C11/4074 ,  G06F11/1068 ,  G11C7/1018 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411 ,  H01L27/10897

Abstract: A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

公开(公告)号：US20190179552A1

公开(公告)日：2019-06-13

申请号：US15837666

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC: G06F3/06 ,  G11C11/4072 ,  G11C11/4091

Abstract: A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US20190172518A1

公开(公告)日：2019-06-06

申请号：US15833713

申请日：2017-12-06

Applicant: Micron Technology, Inc.

Inventor： Yu-Feng Chen ,  Byung S. Moon ,  Myung Ho Bae ,  Harish N. Venkata

IPC: G11C11/4074 ,  G06F13/42 ,  G11C11/408

Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.

公开(公告)号：US10255967B1

公开(公告)日：2019-04-09

申请号：US15824535

申请日：2017-11-28

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C5/14 ,  G11C11/4093 ,  G11C7/10 ,  G11C16/30 ,  G11C29/02 ,  G11C11/56

Abstract: A memory device may include voltage regulation circuitry configured to supply a voltage signal between a high signal and a low signal. The memory device may include a first data line configured to provide a first charge to the voltage regulation circuitry during a first mode of operation of the memory device. The memory device may include a second data line configured to draw a second charge from the voltage regulation circuitry to control a voltage on the second data line during a second mode of operation of the memory device.

公开(公告)号：US20180025759A1

公开(公告)日：2018-01-25

申请号：US15216440

申请日：2016-07-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/08

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.