公开(公告)号：US12086026B2

公开(公告)日：2024-09-10

申请号：US17654354

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：US20240273015A1

公开(公告)日：2024-08-15

申请号：US18440357

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F12/02

CPC classification number: G06F12/0223

Abstract: Described apparatuses and methods provide adaptive selection of a configuration-dependent operand. Adaptive selection enables a die to automatically detect its configuration and dynamically read from or write to configuration-dependent operands of one or more mode registers based on the configuration. In this manner, a memory device with dies having a first byte width (e.g., 1 byte) can be transparent to a memory channel having a second byte width that is larger than the first byte width (e.g., two bytes). For example, two 8-bit dies enabled with aspects of adaptive selection may be coupled to a 16-bit memory channel and each automatically detect its byte position (e.g., upper byte or lower byte). Based on the detected byte position or byte indicator, the 8-bit dies may be configured for use through respective mode registers that correspond to the byte position or assignment of the die.

公开(公告)号：US20240170038A1

公开(公告)日：2024-05-23

申请号：US18511404

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  Kang-Yong Kim

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: Described apparatuses and methods relate to adaptive refresh staggering for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a memory device can include logic that can be programmed to stagger the start of refresh operations for each die upon receiving a command to enter a lower-power mode, such as self-refresh. The staggered start can be implemented at a channel level, a package level, or both. The programming sets a delay for each die so that initiation of refresh operations is staggered. Thus, a first die can initiate refresh operations when a command to enter the lower-power mode is received (e.g., approximately zero delay). However, initiation of refresh operations for subsequent dies (e.g., “after” the first die) is delayed, which can reduce peak current draw and power consumption.

公开(公告)号：US20240070101A1

公开(公告)日：2024-02-29

申请号：US17823415

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20230343380A1

公开(公告)日：2023-10-26

申请号：US17660201

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4085

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US11621031B2

公开(公告)日：2023-04-04

申请号：US17302206

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Sourabh Dhir ,  Keun Soo Song

IPC: G11C5/14 ,  G11C11/4074

Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.

公开(公告)号：US20230039984A1

公开(公告)日：2023-02-09

申请号：US17970460

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee

IPC: G06F13/40 ,  G11C29/50 ,  G11C29/02 ,  H05K1/02 ,  H04L25/02 ,  G06F13/00

Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

公开(公告)号：US20220406357A1

公开(公告)日：2022-12-22

申请号：US17804414

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US11360695B2

公开(公告)日：2022-06-14

申请号：US17022551

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first characteristic and a second memory circuit having a second characteristic. Contact pads of the first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US20220068365A1

公开(公告)日：2022-03-03

申请号：US17459446

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G11C11/406

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.