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    STATUS CHECK USING CHIP ENABLE PIN
    54.
    发明申请
    STATUS CHECK USING CHIP ENABLE PIN 有权

    公开(公告)号：US20230043140A1

    公开(公告)日：2023-02-09

    申请号：US17963773

    申请日：2022-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/16 ,  G06F1/26

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    Sense flags in a memory device
    60.
    发明授权
    Sense flags in a memory device 有权

    公开(公告)号：US11029861B2

    公开(公告)日：2021-06-08

    申请号：US16543743

    申请日：2019-08-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F3/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

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