公开(公告)号：US10515972B2

公开(公告)日：2019-12-24

申请号：US15685878

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US20190244972A1

公开(公告)日：2019-08-08

申请号：US16386544

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/225 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7883

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US10340286B2

公开(公告)日：2019-07-02

申请号：US16103669

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/28

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10283520B2

公开(公告)日：2019-05-07

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L21/225 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11524

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US10256249B2

公开(公告)日：2019-04-09

申请号：US15651719

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20180374860A1

公开(公告)日：2018-12-27

申请号：US16103669

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L21/28282

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10164044B2

公开(公告)日：2018-12-25

申请号：US14688387

申请日：2015-04-16

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

公开(公告)号：US20180019255A1

公开(公告)日：2018-01-18

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L23/532 ,  H01L23/528 ,  H01L21/225

CPC classification number: H01L27/11582 ,  H01L21/225 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7883

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US20170179143A1

公开(公告)日：2017-06-22

申请号：US15450893

申请日：2017-03-06

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H01L27/11556 ,  H01L21/8234

CPC classification number: H01L27/11556 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/11582 ,  H01L29/7827

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

公开(公告)号：US09613973B2

公开(公告)日：2017-04-04

申请号：US14831011

申请日：2015-08-20

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/11582 ,  H01L29/7827

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.