公开(公告)号：US20210073068A1

公开(公告)日：2021-03-11

申请号：US17100571

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Ning Chen ,  Zhengang Chen ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G11C29/52 ,  G06F11/10

Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.

公开(公告)号：US20210043268A1

公开(公告)日：2021-02-11

申请号：US16533498

申请日：2019-08-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F3/06

Abstract: A processing device in a memory sub-system receives a read request from a host system, the read request identifying data stored in a segment of a memory component, and performs a first read operation on the segment of the memory component using a first read voltage level. The processing device determines whether the data stored in the segment of the memory component and read during the first read operation was successfully decoded. Responsive to the data stored in the segment of the memory component and read during the first read operation being successfully decoded, the processing device determines a write-to-read delay time for the segment of the memory component and determines whether the write-to-read delay time for the segment falls within a first write-to-read delay range of a plurality of write-to-read delay ranges for the memory component, wherein the first write-to-read delay range represents a first plurality of write-to-read delay times corresponding to the first read voltage level. Responsive to the write-to-read delay time for the segment not falling within the first write-to-read delay range, the processing device performs a read refresh operation on at least a portion of the segment of the memory component using an applicable read voltage level.

公开(公告)号：US20210012857A1

公开(公告)日：2021-01-14

申请号：US16510483

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/07

Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

公开(公告)号：US20200050383A1

公开(公告)日：2020-02-13

申请号：US16057537

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： Zhenlei E. Shen ,  Zhengang Chen ,  Tingjun Xie ,  Jiangli Zhu

IPC: G06F3/06 ,  G11C13/00

Abstract: Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.

公开(公告)号：US12197743B2

公开(公告)日：2025-01-14

申请号：US17991408

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

公开(公告)号：US20240330105A1

公开(公告)日：2024-10-03

申请号：US18615592

申请日：2024-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Phong S. Nguyen ,  Dung Viet Nguyen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Zhengang Chen

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1068

Abstract: Input data is received for storage by a system. The input data is encoded using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution. The encoded data is then stored on a memory device of the system.

公开(公告)号：US20240264771A1

公开(公告)日：2024-08-08

申请号：US18441911

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/7206 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US11907580B2

公开(公告)日：2024-02-20

申请号：US17645683

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/7206 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US11782787B2

公开(公告)日：2023-10-10

申请号：US17584034

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Zhengang Chen

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0793

Abstract: Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.

公开(公告)号：US11688485B2

公开(公告)日：2023-06-27

申请号：US17443746

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/07

CPC classification number: G11C29/50004 ,  G06F11/073 ,  G11C29/50012 ,  G11C2029/5004

Abstract: A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times