公开(公告)号：US07196548B2

公开(公告)日：2007-03-27

申请号：US10927574

申请日：2004-08-25

申请人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： H03K19/094 ,  H03K17/16

CPC分类号： H03K3/356156 ,  H03K3/356191

摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

公开(公告)号：US07132849B2

公开(公告)日：2006-11-07

申请号：US10852586

申请日：2004-05-24

申请人： John Tucker ,  Ram Krishnamurthy ,  John James Paulos

发明人： John Tucker ,  Ram Krishnamurthy ,  John James Paulos

IPC分类号： G06F7/38 ,  G06F17/50 ,  H03K19/173 ,  H03K19/00

CPC分类号： H03K19/1731

摘要： Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the at least one pin external to the integrated circuit. The external load has at least two discrete values. A voltage detector detects the voltage on the at least one pin and a state detector then compares the voltage on the at least one pin to at least two discrete voltage thresholds. Each of the discrete voltages is associated with a separate value of a control word, and the state detector is operable to determine the value of the control word associated with the detected voltage. The state detector then outputs the determined value of the control word.

公开(公告)号：US20060133183A1

公开(公告)日：2006-06-22

申请号：US11018012

申请日：2004-12-20

申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C11/56

摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

摘要翻译： 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。

公开(公告)号：US06992603B2

公开(公告)日：2006-01-31

申请号：US10813084

申请日：2004-03-31

申请人： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

发明人： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

IPC分类号： H03M7/00

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

摘要翻译： 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US06690604B2

公开(公告)日：2004-02-10

申请号：US10024901

申请日：2001-12-18

申请人： Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

发明人： Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.

摘要翻译： 存储器电路，例如高速缓存或寄存器文件，其中保持器功能单元被数字地控制以补偿可变的亚阈值泄漏电流。

公开(公告)号：US20190057727A1

公开(公告)日：2019-02-21

申请号：US16160955

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G11C7/10 ,  G11C5/04 ,  G06F12/06

摘要： Techniques and mechanisms for configuring a memory device to perform a sequence of in-memory computations. In an embodiment, a memory device includes a memory array and circuitry, coupled thereto, to perform data computations based on the data stored at the memory array. Based on instructions received at the memory device, control circuitry is configured to enable an automatic performance of a sequence of operations. In another embodiment, the memory device is coupled in an in-series arrangement of other memory devices to provide a pipeline circuit architecture. The memory devices each function as a respective stage of the pipeline circuit architecture, where the stages each perform respective in-memory computations. Some or all such stages each provide a different respective layer of a neural network.

公开(公告)号：US20190057304A1

公开(公告)日：2019-02-21

申请号：US16160800

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06N3/063 ,  G06N3/04

摘要： The present disclosure is directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

公开(公告)号：US09544141B2

公开(公告)日：2017-01-10

申请号：US13996544

申请日：2011-12-29

申请人： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

发明人： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

IPC分类号： H04L29/06 ,  H04L9/08

CPC分类号： H04L9/0891 ,  G09C1/00 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L2209/12

摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.

摘要翻译： 本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置。 处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。 硬件密钥可用于加密诸如秘密密钥的密钥。 加密密钥可以存储在处理器的存储器中。 可以验证加密的密钥。 可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

公开(公告)号：US07477171B2

公开(公告)日：2009-01-13

申请号：US11729191

申请日：2007-03-27

申请人： Sanu K. Mathew ,  Ram Krishnamurthy

发明人： Sanu K. Mathew ,  Ram Krishnamurthy

IPC分类号： H03M7/04

CPC分类号： H03M7/12

摘要： Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

摘要翻译： 本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

公开(公告)号：US20080238736A1

公开(公告)日：2008-10-02

申请号：US11729191

申请日：2007-03-27

申请人： Sanu K. Mathew ,  Ram Krishnamurthy

发明人： Sanu K. Mathew ,  Ram Krishnamurthy

IPC分类号： H03M7/12

CPC分类号： H03M7/12

摘要： Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

摘要翻译： 本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。