摘要:
An optical transmission system is provided, which permits high-precision optical transmission of a signal even if the signal has a high accurate timing, an indefinite period, and a DC component. The transmitting side is provided with a rise edge detecting circuit 1 for detecting the rise edge of a transmitting signal waveform, a transmitting pulse generating circuit 2 for generating a transmitting pulse signal (b) constituted by a pair of opposite-polarity pulses inverting their polarities at the detected timing, and a light intensity modulation circuit 3 for generating a light intensity modulated signal (c) based on the pulse signal (b). The receiving side is provided with an AC-coupled receiving circuit 4 for receiving the light intensity modulated signal (c) and extracting therefrom only an AC component, and a discrimination circuit 5 for discriminating the rise timing from the received signal. Further, a similar arrangement is provided for transmitting a signal associated with the fall edge of the transmitting signal waveform. On the basis of the discriminated rise timing and the fall timing, the rise edge and the fall edge of the original transmitting signal waveform are regenerated.
摘要:
A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.
摘要:
An optical transmission system is provided, which permits high-precision optical transmission of a signal even if the signal has a high accurate timing, an indefinite period, and a DC component. The transmitting side is provided with a rise edge detecting circuit 1 for detecting the rise edge of a transmitting signal waveform, a transmitting pulse generating circuit 2 for generating a transmitting pulse signal (b) constituted by a pair of opposite-polarity pulses inverting their polarities at the detected timing, and a light intensity modulation circuit 3 for generating a light intensity modulated signal (c) based on the pulse signal (b). The receiving side is provided with an AC-coupled receiving circuit 4 for receiving the light intensity modulated signal (c) and extracting therefrom only an AC component, and a discrimination circuit 5 for discriminating the rise timing from the received signal. Further, a similar arrangement is provided for transmitting a signal associated with the fall edge of the transmitting signal waveform. On the basis of the discriminated rise timing and the fall timing, the rise edge and the fall edge of the original transmitting signal waveform are regenerated.
摘要:
A CMOS integrated circuit for use in a semiconductor test system generates timing signals of high timing resolution and accuracy for testing semiconductor devices. The CMOS integrated circuit includes a heater circuit for generating heat based on electric current flowing there through, and a heater control circuit for detecting an amount of total electric current flowing through a timing generator block for generating timing signals, and a control circuit block for providing timing data to the timing generator block, and the heater circuit, and providing a control voltage to the heater circuit based on the amount of current detected to control the current flowing through the heater circuit through a negative feedback loop.
摘要:
A timing correcting method for correcting the timings of an IC tester at low cost, wherein the method uses a probe (300) for taking out a signal fed to a pin out of the pins of an IC socket (203) to which an IC to be measured is plugged when the probe is brought into contact with the pin and supplying a correcting pulse to the pin, and the timing of the correcting pulse taken in by a reference comparator (CP-RF) provided in the probe and the timing of a reference correcting pulse applied to an IC socket from a reference driver (DR-RF) provided in the probe are measured by a timing measuring function that the IC tester has, thus performing timing correction.
摘要:
A CMOS integrated circuit to be used in a semiconductor test system for generating timing signals of high timing resolution and accuracy for testing semiconductor devices. The CMOS integrated circuit includes a heater circuit for generating heat based on electric current flowing there through, and a heater control circuit for detecting an amount of total electric current flowing through a timing generator block for generating timing signals, a control circuit block for providing timing data to the timing generator block, and the heater circuit and providing a control voltage to the heater circuit based on the amount of total current detected to control the current flowing through the heater circuit through a negative feedback loop.
摘要:
A semiconductor device driven by two power source voltages VDD and VSS (VDD>VSS) comprising a base, and an FET provided on the base. The FET has a gate, a source, a drain, and a substrate; and the gate is connected to one of the two power source voltages VDD and VSS, and at least one of the source, the drain, or the substrate is connected to another of the two power source voltages VDD and VSS. A capacity coupling is formed between the power source voltage VDD and the power source voltage VSS by a capacitance generated between the gate and at least one of the source, the drain, and the substrate.
摘要:
An optical fiber-embedded layer is provided as one layer of a multiple-layered electrical wiring board comprising a mother board having an electrical circuit mounted therein. The optical fiber-embedded layer is formed through its surface with an aperture to expose first ends of the optical fibers where a 45° reflecting surface is provided so that the light exiting from the optical fibers is reflected in a direction orthogonal to the plane of the wiring board and input into the ends of optical fibers at an end face of a daughter board. Light exiting from the ends of optical fibers at the end face of the daughter board and entering the 45° reflecting surface may be input into the optical fibers in the optical fiber-embedded layer.
摘要:
A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.
摘要:
A timing signal generator generates timing signals having a timing resolution higher than a reference clock signal and can measure a delay time in the timing signal generator with high accuracy by a loop oscillation method. The timing signal generator includes: a phase lock loop having a variable delay circuit which is formed of a plurality of delay elements connected in series wherein a delay time in the variable delay circuit is phase locked with a clock signal, a track hold circuit provided in the phase lock loop to transfer a phase lock control voltage to the phase lock loop in a phase lock mode and to temporarily hold the control voltage in a loop oscillation mode, a selector circuit to select a timing signal from a plurality of signals corresponding to the plurality of delay elements to produce the timing signal at a timing output, an input selector for selectively providing the clock signal to the phase lock loop during the phase lock mode and a returning pulse from the timing output during the loop oscillation mode, and a pulse injection circuit for starting an oscillation in the closed loop by injecting a pulse signal in the closed loop.