Optical pulse transmission system, optical pulse transmitting method and optical pulse detection method
    51.
    发明授权
    Optical pulse transmission system, optical pulse transmitting method and optical pulse detection method 失效
    光脉冲传输系统,光脉冲发射方式和光脉冲检测方法

    公开(公告)号:US06819876B2

    公开(公告)日:2004-11-16

    申请号:US09960153

    申请日:2001-09-20

    IPC分类号: H04B1000

    摘要: An optical transmission system is provided, which permits high-precision optical transmission of a signal even if the signal has a high accurate timing, an indefinite period, and a DC component. The transmitting side is provided with a rise edge detecting circuit 1 for detecting the rise edge of a transmitting signal waveform, a transmitting pulse generating circuit 2 for generating a transmitting pulse signal (b) constituted by a pair of opposite-polarity pulses inverting their polarities at the detected timing, and a light intensity modulation circuit 3 for generating a light intensity modulated signal (c) based on the pulse signal (b). The receiving side is provided with an AC-coupled receiving circuit 4 for receiving the light intensity modulated signal (c) and extracting therefrom only an AC component, and a discrimination circuit 5 for discriminating the rise timing from the received signal. Further, a similar arrangement is provided for transmitting a signal associated with the fall edge of the transmitting signal waveform. On the basis of the discriminated rise timing and the fall timing, the rise edge and the fall edge of the original transmitting signal waveform are regenerated.

    摘要翻译: 提供了一种光传输系统,即使信号具有高准确的定时,不确定的周期和直流分量,也允许信号的高精度光传输。 发送侧设置有用于检测发送信号波形的上升沿的上升沿检测电路1,发送脉冲发生电路2,用于生成由一对反转极性的反极性脉冲构成的发送脉冲信号(b) 以及用于基于脉冲信号(b)产生光强度调制信号(c)的光强度调制电路3。 接收侧设置有用于接收光强度调制信号(c)并仅从其中提取AC分量的AC耦合接收电路4,以及用于从接收信号中鉴别上升时间的判别电路5。 此外,提供了用于发送与发送信号波形的下降沿相关联的信号的类似布置。 基于鉴别上升时间和下降时间,原始发送信号波形的上升沿和下降沿被再生。

    Delay clock generating apparatus and delay time measuring apparatus
    52.
    发明授权
    Delay clock generating apparatus and delay time measuring apparatus 失效
    延迟时钟发生装置和延迟时间测量装置

    公开(公告)号:US06807243B2

    公开(公告)日:2004-10-19

    申请号:US10421497

    申请日:2003-04-23

    IPC分类号: H04L2538

    CPC分类号: H03L7/0995 G01R31/31922

    摘要: A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.

    摘要翻译: 标准时钟34输入到相位比较器52和相位控制器56.环形振荡器50振荡具有与标准时钟34相同周期的移位时钟70.相位比较器52将移位时钟70的向下移位与 标准时钟34向下移动以输出移位时钟72.移位时钟72被提供给脉冲插入器54.相位控制器56接收标准时钟34并产生指示移位时钟72的周期的相位控制信号74 插入脉冲在移位时钟72的多个周期之间插入到其中。脉冲插入器54将插入脉冲插入由相位控制信号74指示的移位时钟的周期。相位锁定单元58产生 通过基于标准时钟和包括插入脉冲的移位时钟76,延迟由环形振荡器50相对于标准时钟的相位振荡的移位时钟70的相位的延迟时钟82。

    Optical pulse transmission system, optical pulse transmitting method and optical pulse detecting method
    53.
    发明授权
    Optical pulse transmission system, optical pulse transmitting method and optical pulse detecting method 失效
    光脉冲传输系统,光脉冲发射方式和光脉冲检测方法

    公开(公告)号:US06778783B2

    公开(公告)日:2004-08-17

    申请号:US09957952

    申请日:2001-09-21

    IPC分类号: H04B1000

    摘要: An optical transmission system is provided, which permits high-precision optical transmission of a signal even if the signal has a high accurate timing, an indefinite period, and a DC component. The transmitting side is provided with a rise edge detecting circuit 1 for detecting the rise edge of a transmitting signal waveform, a transmitting pulse generating circuit 2 for generating a transmitting pulse signal (b) constituted by a pair of opposite-polarity pulses inverting their polarities at the detected timing, and a light intensity modulation circuit 3 for generating a light intensity modulated signal (c) based on the pulse signal (b). The receiving side is provided with an AC-coupled receiving circuit 4 for receiving the light intensity modulated signal (c) and extracting therefrom only an AC component, and a discrimination circuit 5 for discriminating the rise timing from the received signal. Further, a similar arrangement is provided for transmitting a signal associated with the fall edge of the transmitting signal waveform. On the basis of the discriminated rise timing and the fall timing, the rise edge and the fall edge of the original transmitting signal waveform are regenerated.

    摘要翻译: 提供了一种光传输系统,即使信号具有高准确的定时,不确定的周期和直流分量,也允许信号的高精度光传输。 发送侧设置有用于检测发送信号波形的上升沿的上升沿检测电路1,发送脉冲发生电路2,用于生成由一对反转极性的反极性脉冲构成的发送脉冲信号(b) 以及用于基于脉冲信号(b)产生光强度调制信号(c)的光强度调制电路3。 接收侧设置有用于接收光强度调制信号(c)并仅从其中提取AC分量的AC耦合接收电路4,以及用于从接收信号中鉴别上升时间的判别电路5。 此外,提供了用于发送与发送信号波形的下降沿相关联的信号的类似布置。 基于鉴别上升时间和下降时间,原始发送信号波形的上升沿和下降沿被再生。

    CMOS integrated circuit and timing signal generator using same
    54.
    发明授权
    CMOS integrated circuit and timing signal generator using same 失效
    CMOS集成电路和定时信号发生器使用相同

    公开(公告)号:US06590405B2

    公开(公告)日:2003-07-08

    申请号:US10092997

    申请日:2002-03-05

    申请人: Toshiyuki Okayasu

    发明人: Toshiyuki Okayasu

    IPC分类号: G01R3102

    CPC分类号: G01R31/31922

    摘要: A CMOS integrated circuit for use in a semiconductor test system generates timing signals of high timing resolution and accuracy for testing semiconductor devices. The CMOS integrated circuit includes a heater circuit for generating heat based on electric current flowing there through, and a heater control circuit for detecting an amount of total electric current flowing through a timing generator block for generating timing signals, and a control circuit block for providing timing data to the timing generator block, and the heater circuit, and providing a control voltage to the heater circuit based on the amount of current detected to control the current flowing through the heater circuit through a negative feedback loop.

    摘要翻译: 用于半导体测试系统的CMOS集成电路产生用于测试半导体器件的高定时分辨率和精度的定时信号。 CMOS集成电路包括:加热器电路,用于根据通过其流过的电流产生热;以及加热器控制电路,用于检测流过定时发生器块的总电流量以产生定时信号;以及控制电路块,用于提供 定时数据发送到定时发生器块和加热器电路,并且基于检测到的电流量向加热器电路提供控制电压,以通过负反馈回路控制流过加热器电路的电流。

    Method for correcting timing for IC tester and IC tester having correcting function using the correcting method
    55.
    发明授权
    Method for correcting timing for IC tester and IC tester having correcting function using the correcting method 失效
    使用该校正方法校正具有校正功能的IC测试器和IC测试器的定时的方法

    公开(公告)号:US06586924B1

    公开(公告)日:2003-07-01

    申请号:US09806072

    申请日:2001-03-23

    IPC分类号: G01R104

    CPC分类号: G01R31/3191

    摘要: A timing correcting method for correcting the timings of an IC tester at low cost, wherein the method uses a probe (300) for taking out a signal fed to a pin out of the pins of an IC socket (203) to which an IC to be measured is plugged when the probe is brought into contact with the pin and supplying a correcting pulse to the pin, and the timing of the correcting pulse taken in by a reference comparator (CP-RF) provided in the probe and the timing of a reference correcting pulse applied to an IC socket from a reference driver (DR-RF) provided in the probe are measured by a timing measuring function that the IC tester has, thus performing timing correction.

    摘要翻译: 一种用于以低成本校正IC测试仪的定时的定时校正方法,其中该方法使用探针(300)将从IC插座(203)的引脚输出的信号输出到IC 当探针与引脚接触并且向引脚提供校正脉冲时,被测量被插入,并且由设置在探头中的参考比较器(CP-RF)所接收的校正脉冲的定时和定时 通过IC测试仪具有的定时测量功能来测量从设置在探头中的参考驱动器(DR-RF)施加到IC插座的参考校正脉冲,从而执行定时校正。

    CMOS integrated circuit and timing signal generator using same
    56.
    发明授权
    CMOS integrated circuit and timing signal generator using same 失效
    CMOS集成电路和定时信号发生器使用相同

    公开(公告)号:US06433567B1

    公开(公告)日:2002-08-13

    申请号:US09557915

    申请日:2000-04-21

    申请人: Toshiyuki Okayasu

    发明人: Toshiyuki Okayasu

    IPC分类号: G01R3102

    CPC分类号: G01R31/31922

    摘要: A CMOS integrated circuit to be used in a semiconductor test system for generating timing signals of high timing resolution and accuracy for testing semiconductor devices. The CMOS integrated circuit includes a heater circuit for generating heat based on electric current flowing there through, and a heater control circuit for detecting an amount of total electric current flowing through a timing generator block for generating timing signals, a control circuit block for providing timing data to the timing generator block, and the heater circuit and providing a control voltage to the heater circuit based on the amount of total current detected to control the current flowing through the heater circuit through a negative feedback loop.

    摘要翻译: 一种用于半导体测试系统的CMOS集成电路,用于产生用于测试半导体器件的高定时分辨率和精度的定时信号。 CMOS集成电路包括:加热器电路,用于根据流过该电流的电流产生热;以及加热器控制电路,用于检测流过定时发生器块的总电流量以产生定时信号;控制电路块,用于提供定时 数据发送到定时发生器模块和加热器电路,并且基于检测到的总电流量向加热器电路提供控制电压,以通过负反馈回路控制流过加热器电路的电流。

    Semiconductor device having capacitor that reduce fluctuation of power supply
    57.
    发明授权
    Semiconductor device having capacitor that reduce fluctuation of power supply 失效
    具有减小电源波动的电容器的半导体装置

    公开(公告)号:US06268757B1

    公开(公告)日:2001-07-31

    申请号:US09431094

    申请日:1999-11-01

    申请人: Toshiyuki Okayasu

    发明人: Toshiyuki Okayasu

    IPC分类号: H03K1716

    摘要: A semiconductor device driven by two power source voltages VDD and VSS (VDD>VSS) comprising a base, and an FET provided on the base. The FET has a gate, a source, a drain, and a substrate; and the gate is connected to one of the two power source voltages VDD and VSS, and at least one of the source, the drain, or the substrate is connected to another of the two power source voltages VDD and VSS. A capacity coupling is formed between the power source voltage VDD and the power source voltage VSS by a capacitance generated between the gate and at least one of the source, the drain, and the substrate.

    摘要翻译: 由两个电源电压VDD和VSS(VDD> VSS)驱动的半导体器件包括基极和设置在基极上的FET。 FET具有栅极,源极,漏极和衬底; 并且栅极连接到两个电源电压VDD和VSS中的一个,并且源极,漏极或衬底中的至少一个连接到两个电源电压VDD和VSS中的另一个。 通过在栅极和源极,漏极和衬底中的至少一个之间产生的电容,在电源电压VDD和电源电压VSS之间形成电容耦合。

    Opitcal/electrical hybrid wiring board and its manufacturing method
    58.
    发明授权
    Opitcal/electrical hybrid wiring board and its manufacturing method 失效
    Opitcal /电气混合布线板及其制造方法

    公开(公告)号:US06257771B1

    公开(公告)日:2001-07-10

    申请号:US09077989

    申请日:1998-06-12

    申请人: Toshiyuki Okayasu

    发明人: Toshiyuki Okayasu

    IPC分类号: G02B643

    摘要: An optical fiber-embedded layer is provided as one layer of a multiple-layered electrical wiring board comprising a mother board having an electrical circuit mounted therein. The optical fiber-embedded layer is formed through its surface with an aperture to expose first ends of the optical fibers where a 45° reflecting surface is provided so that the light exiting from the optical fibers is reflected in a direction orthogonal to the plane of the wiring board and input into the ends of optical fibers at an end face of a daughter board. Light exiting from the ends of optical fibers at the end face of the daughter board and entering the 45° reflecting surface may be input into the optical fibers in the optical fiber-embedded layer.

    摘要翻译: 光纤嵌入层设置为包括安装有电路的母板的多层电布线板的一层。 光纤嵌入层通过其表面形成有孔,以露出光纤的第一端,其中设置有45°的反射表面,使得从光纤出射的光在垂直于该光纤的平面的方向上被反射 接线板,并在子板的端面处输入光纤端部。 从子板的端面处的光纤末端出射并进入45°反射面的光可以输入到光纤嵌入层的光纤中。

    Signal transmission circuit achieving significantly improved response
time of a driven circuit, CMOS semiconductor device and circuit board
therefor
    59.
    发明授权
    Signal transmission circuit achieving significantly improved response time of a driven circuit, CMOS semiconductor device and circuit board therefor 有权
    信号传输电路实现了驱动电路,CMOS半导体器件及其电路板的响应时间的显着改善

    公开(公告)号:US6166575A

    公开(公告)日:2000-12-26

    申请号:US137163

    申请日:1998-08-20

    申请人: Toshiyuki Okayasu

    发明人: Toshiyuki Okayasu

    CPC分类号: H03K19/00361 H03K19/01707

    摘要: A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.

    摘要翻译: 信号传输电路,CMOS半导体器件和电路板改善了当信号线较长或时间较长时,在大规模集成电路内部的长信号线上产生的具有大电容的信号线的信号传输特性 许多驱动电路连接到信号线。 输出驱动电路和驱动电路的电源电压的中点电压。 然后将具有低输出阻抗的辅助电路连接到信号线。 因此,信号线的电压被保持在电源电压的中点电压。 同时,从驱动电路输出的驱动信号以小幅度的中点电压(被驱动电路的阈值电压)为中心进行激励。 然后驱动电路被限制在小幅度的该驱动信号驱动。

    Test signal generator having timing calibration circuit
    60.
    发明授权
    Test signal generator having timing calibration circuit 失效
    具有定时校准电路的测试信号发生器

    公开(公告)号:US5712582A

    公开(公告)日:1998-01-27

    申请号:US667399

    申请日:1996-06-21

    摘要: A timing signal generator generates timing signals having a timing resolution higher than a reference clock signal and can measure a delay time in the timing signal generator with high accuracy by a loop oscillation method. The timing signal generator includes: a phase lock loop having a variable delay circuit which is formed of a plurality of delay elements connected in series wherein a delay time in the variable delay circuit is phase locked with a clock signal, a track hold circuit provided in the phase lock loop to transfer a phase lock control voltage to the phase lock loop in a phase lock mode and to temporarily hold the control voltage in a loop oscillation mode, a selector circuit to select a timing signal from a plurality of signals corresponding to the plurality of delay elements to produce the timing signal at a timing output, an input selector for selectively providing the clock signal to the phase lock loop during the phase lock mode and a returning pulse from the timing output during the loop oscillation mode, and a pulse injection circuit for starting an oscillation in the closed loop by injecting a pulse signal in the closed loop.

    摘要翻译: 定时信号发生器产生具有比参考时钟信号高的定时分辨率的定时信号,并且可以通过环路振荡方法以高精度测量定时信号发生器中的延迟时间。 定时信号发生器包括:具有可变延迟电路的锁相环,该可变延迟电路由串联连接的多个延迟元件形成,其中可变延迟电路中的延迟时间与时钟信号锁相,轨道保持电路设置在 锁相环,以锁相模式将锁相控制电压传递给锁相环,并以环路振荡模式临时保持控制电压;选择电路,从对应于多个信号的多个信号中选择定时信号; 多个延迟元件,用于在定时输出端产生定时信号;输入选择器,用于在锁相模式期间选择性地将时钟信号提供给锁相环,以及在环路振荡模式期间来自定时输出的返回脉冲,以及脉冲 注入电路,用于通过在闭环中注入脉冲信号来在闭环中启动振荡。