公开(公告)号：US20050169091A1

公开(公告)日：2005-08-04

申请号：US11049059

申请日：2005-02-03

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C8/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

摘要翻译： 触发产生电路提供触发信号。 延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。 时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。 确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。 延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

公开(公告)号：US06859415B2

公开(公告)日：2005-02-22

申请号：US10352218

申请日：2003-01-28

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

公开(公告)号：US06813211B2

公开(公告)日：2004-11-02

申请号：US10342289

申请日：2003-01-15

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C8/18 ,  G11C11/406 ,  G11C11/408

摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

摘要翻译： 响应于地址转换检测信号的前沿和后沿来控制用于控制存储器单元选择操作的内部正常行激活信号的激活/去激活。 当内部正常行激活信号被激活时，地址转换检测信号的产生被掩码电路掩蔽。 可以防止激活操作和正常行激活信号的失活操作之间的冲突，并且可以稳定地执行内部操作。 提供了一种具有与静态随机存取存储器兼容并且能够稳定地执行内部操作的接口的无刷新的动态半导体存储器件。

公开(公告)号：US06795943B2

公开(公告)日：2004-09-21

申请号：US09973894

申请日：2001-10-11

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

IPC分类号： G01R3128

CPC分类号： G11C29/14

摘要： A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

摘要翻译： 半导体存储器包括：第一解码器，根据第一至第四数据信号选择测试模式B的模式1-n中的任何一个;以及第二解码器，根据第五至第八数据信号选择测试模式B的模式1-n中的任何一个 。 当在测试模式A中未设置预定模式m + 1时，设置由第一和第二解码器选择的模式。 当设定了预定模式m + 1时，设置由第一解码器选择的模式。 因此，通过将四个数据输入/输出端子连接到测试器，可以在制造商侧设置测试模式B.

公开(公告)号：US06744679B2

公开(公告)日：2004-06-01

申请号：US10244026

申请日：2002-09-16

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Takafumi Takatsuka

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Takafumi Takatsuka

IPC分类号： G11C700

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/229

摘要： A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.

摘要翻译： 如果列激活信号ZCOLRE通过改变内部地址Add而被激活，则DRAM执行数据写入，然后通过从外部产生写信号WE来激活内部写控制信号WDRV。 然而，为了解决在某些情况下在可选定时执行数据写入的情况下不进行数据写入的问题，根据本发明的半导体存储器件包括延迟单元，从而延迟内部写入控制的输出 信号WDRV直到列激活信号ZCOLRE被激活，即使当产生写入信号WE时。

公开(公告)号：US06721225B2

公开(公告)日：2004-04-13

申请号：US10252565

申请日：2002-09-24

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11406

CPC分类号： G11C11/406

摘要： A semiconductor memory device according to the invention has an active state where data can be read and written and a standby state where the data are retained. It has a memory cell array including a plurality of memory cells arranged in a matrix, and a refresh controller which refreshes data stored in the plurality of memory cells. In the refresh controller, a first refresh cycle generator generates a first refresh cycle, while a second refresh cycle generator generates a second refresh cycle having a period shorter than the first refresh cycle. A refresh processor performs refresh operation when the refresh operation becomes possible after the first refresh cycle and, when refresh operation is not performed for a longer period than the first refresh cycle, it performs refresh operations successively based on the second refresh cycle in the longer period or after the end of the longer period.

摘要翻译： 根据本发明的半导体存储器件具有可读取和写入数据的活动状态以及数据被保留的待机状态。 它具有包括排列成矩阵的多个存储单元的存储单元阵列和刷新存储在多个存储单元中的数据的刷新控制器。 在刷新控制器中，第一刷新周期发生器产生第一刷新周期，而第二刷新周期发生器产生具有比第一刷新周期短的周期的第二刷新周期。 当刷新操作在第一刷新周期之后变为可能时，刷新处理器执行刷新操作，并且当刷新操作不比第一刷新周期更长的时间执行时，它在较长时间段内基于第二刷新周期连续执行刷新操作 或者在较长时期结束之后。

公开(公告)号：US06584013B2

公开(公告)日：2003-06-24

申请号：US09982792

申请日：2001-10-22

申请人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

发明人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

IPC分类号： G11C1134

CPC分类号： G11C11/005

摘要： A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

公开(公告)号：US06577553B2

公开(公告)日：2003-06-10

申请号：US10123167

申请日：2002-04-17

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2207/2227

摘要： Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

公开(公告)号：US06331958B1

公开(公告)日：2001-12-18

申请号：US09725856

申请日：2000-11-30

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C700

摘要： A semiconductor memory device according to the present invention includes a memory core portion, a test mode control circuit for transmitting data output from the memory core portion to an internal node, and a data input/output control circuit for inputting/outputting in series a plurality of pieces of parallel data input/output to each internal node to a data node. The test mode control circuit transmits read data from the memory core portion as it is to the internal node in a normal reading operation, and compresses data output from the memory core portion on the basis of a prescribed unit and transmits the data to the internal node in a test mode. Therefore, the test data compressed for each prescribed unit can be input/output by using a smaller number of data nodes in the test mode than in the normal operation mode.

公开(公告)号：US06205067B1

公开(公告)日：2001-03-20

申请号：US09480498

申请日：2000-01-11

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C2900

CPC分类号： G11C29/06 ,  G11C5/00 ,  G11C11/401 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/34 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/2602

摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

摘要翻译： 压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。 对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线 字线到选定状态。 可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。 在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。