公开(公告)号：US06518154B1

公开(公告)日：2003-02-11

申请号：US09813310

申请日：2001-03-21

申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.

摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如， ，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。 本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

公开(公告)号：US06452250B1

公开(公告)日：2002-09-17

申请号：US09488289

申请日：2000-01-20

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L2900

CPC分类号： H01G2/065 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a planar capacitor positioned adjacent to a logic circuit implemented on a silicon die. The silicon die is bonded to a mounting base using controlled collapse chip connection methods such that a ground terminal of the silicon die is coupled to a ground trace in the mounting base and a Vdd terminal of the silicon die is coupled to a Vdd trace in the mounting base. The capacitor includes via structures with controlled collapse chip connection structures for bonding to the mounting base directly above the silicon die and coupling a first charge accumulation plate to the Vdd trace and a second charge accumulation plate to the ground trace.

摘要翻译： 集成电路结构包括与实现在硅芯片上的逻辑电路相邻的平面电容器。 使用受控的崩溃芯片连接方法将硅晶片结合到安装基座，使得硅晶片的接地端子耦合到安装基座中的接地迹线，并且硅晶片的Vdd端子耦合到Vdd迹线 安装底座。 该电容器包括具有可控的崩溃芯片连接结构的通孔结构，用于将直接在硅芯片上方的安装基座接合，并将第一电荷累积板耦合到Vdd迹线，并将第二电荷累积板耦合到接地迹线。

公开(公告)号：US06403492B1

公开(公告)日：2002-06-11

申请号：US09776307

申请日：2001-02-02

申请人： Matthew S. Buynoski ,  Darin A. Chan

发明人： Matthew S. Buynoski ,  Darin A. Chan

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

摘要： A method of trench isolation includes removal of insulation material after planarization of the insulation material and before stripping of a nitride layer such as polish stop layer. The removal of insulation material may be accomplished, for example, by etching. The amount of material removed may be selected so that a surface of the device is substantially planar after one or more subsequent processing steps.

摘要翻译： 沟槽隔离的方法包括在绝缘材料平坦化之后以及剥离诸如抛光停止层之类的氮化物层之前去除绝缘材料。 绝缘材料的去除可以例如通过蚀刻来实现。 可以选择去除的材料的量，使得在一个或多个后续处理步骤之后，该装置的表面基本上是平面的。

公开(公告)号：US06368950B1

公开(公告)日：2002-04-09

申请号：US09734186

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28097

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

公开(公告)号：US06342414B1

公开(公告)日：2002-01-29

申请号：US09734189

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L218238

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低 温度金属硅化物门。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06265253B1

公开(公告)日：2001-07-24

申请号：US09305098

申请日：1999-05-05

申请人： Todd Lukanc ,  Matthew S. Buynoski ,  Zicheng Gary Ling

发明人： Todd Lukanc ,  Matthew S. Buynoski ,  Zicheng Gary Ling

IPC分类号： H01L218238

CPC分类号： H01L21/823864

摘要： Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and aluminum disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum disposable spacers removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using aluminum disposable spacers, which can be easily formed and removed without damage to other structures on the substrate, the critical masking steps for source/drain ion implantation are reduced to two, thereby reducing production costs and increasing manufacturing throughput. By employing sidewall spacers, impurities are prevented from being implanted at the edges of the gates. Thus, when source/drain junctions are formed, as by heating and diffusing the implanted impurities, they are advantageously located proximal to the gate edges, and not under the gates, thereby improving device performance.

摘要翻译： 具有优化的连接位置的不同导电类型的半导体器件使用最少数量的临界掩模形成在半导体衬底上。 实施例包括在半导体衬底的主表面上形成导电栅极，在栅极的侧表面上的侧壁间隔物和侧壁间隔物上的铝一次性间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，去除未屏蔽的栅极上的侧壁间隔物上的铝一次性间隔物，并且形成第二杂质类型的轻或中等掺杂的源极/漏极延伸植入物 底物。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，去除剩余的铝一次性间隔物，并形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。 通过使用可以容易地形成和去除的铝一次性间隔件，而不损坏衬底上的其它结构，源/漏离子注入的关键掩蔽步骤减少到两个，从而降低生产成本并提高制造生产量。 通过使用侧壁间隔物，防止杂质被植入门的边缘。 因此，当形成源极/漏极结时，通过加热和扩散植入的杂质，它们有利地位于栅极边缘附近，而不在栅极下方，从而提高器件性能。

公开(公告)号：US06221706B1

公开(公告)日：2001-04-24

申请号：US09268713

申请日：1999-03-17

申请人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling ,  Matthew S. Buynoski

发明人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling ,  Matthew S. Buynoski

IPC分类号： H01L218238

CPC分类号： H01L21/823864

摘要： MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable aluminum sidewall spacers, which can be easily formed and removed without damage to other structures on the substrate or to the substrate silicon, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

摘要翻译： 使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的MOS半导体器件。 实施例包括在半导体衬底的主表面上形成导电栅极和在栅极的侧表面上的一次性铝侧壁间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的铝侧壁间隔物，并且在第二杂质类型中形成轻度或中度掺杂的第二杂质类型的源极/漏极延伸植入物 基质。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源/漏植入物，除去剩余的铝侧壁间隔物，形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。 通过使用可以容易地形成和去除而不损坏衬底或衬底硅上的其它结构的一次性铝侧壁间隔物，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并增加 制造吞吐量。

公开(公告)号：US06218282B1

公开(公告)日：2001-04-17

申请号：US09252184

申请日：1999-02-18

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L214763

CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L23/3171 ,  H01L23/5222 ,  H01L2924/0002 ,  Y10T29/49155 ,  H01L2924/00

摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and chemical vapor depositing W to line the interconnection system. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, depositing W by CVD to line the interconnection system and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.

摘要翻译： 通过去除层间电介质和化学气相沉积W以对互连系统进行排列，多级半导体器件形成具有降低的寄生电容，而不牺牲结构完整性或电迁移性能。 实施例包括在形成第一金属化水平之前沉积介电密封层，例如氮化硅，在形成最后的金属化水平之后去除层间电介质，通过CVD沉积W以使互连系统排列并形成介电保护层，例如， 硅烷衍生的氧化物最底层的保护层，最上层的金属化层。

公开(公告)号：US06194299B1

公开(公告)日：2001-02-27

申请号：US09325021

申请日：1999-06-03

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/4941 ,  H01L29/6659

摘要： The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the silicide over the polysilicon or the polysilicon of the gate is exposed. The present invention further includes the step of etching away the silicide and a predetermined thickness of the polysilicon if the silicide is exposed and of etching away a predetermined thickness of the polysilicon if the polysilicon is exposed, such that an opening is formed on top of a remaining portion of the polysilicon. In addition, the present invention includes the step of depositing a metal within the opening. In this manner, the gate of the present invention has low resistivity since a relatively thick layer of metal is deposited on the remaining portion of the polysilicon. However, with the present invention, the remaining portion of the polysilicon has a sufficient thickness such that a threshold voltage of the MOSFET is not substantially affected by the metal disposed on top of the remaining portion of the polysilicon.

摘要翻译： 本发明是一种用于制造具有低电阻率的栅极的MOSFET（金属氧化物半导体场效应晶体管）的栅极的方法。 MOSFET具有在半导体衬底内制造的漏极区域，源极区域和沟道区域，并且MOSFET最初在沟道区域上具有由设置在栅极电介质上的多晶硅上的硅化物构成的栅极。 通常，本发明的方法包括在MOSFET的漏极区域，源极区域和栅极之上沉积第一介电层的步骤。 本发明还包括在漏极区域和源极区域上抛光第一电介质层并且在栅极上抛光第一电介质层直至硅化物超过多晶硅或栅极的多晶硅的步骤。 本发明还包括如果硅化物被暴露则蚀刻掉硅化物和预定厚度的多晶硅的步骤，并且如果多晶硅被暴露则蚀刻掉预定厚度的多晶硅，使得开口形成在 剩余部分的多晶硅。 此外，本发明包括在开口内沉积金属的步骤。 以这种方式，本发明的栅极具有低电阻率，因为相对较厚的金属层沉积在多晶硅的剩余部分上。 然而，利用本发明，多晶硅的剩余部分具有足够的厚度，使得MOSFET的阈值电压基本上不受设置在多晶硅的剩余部分顶部的金属的影响。

公开(公告)号：US5729045A

公开(公告)日：1998-03-17

申请号：US626340

申请日：1996-04-02

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036

CPC分类号： H01L29/66575 ,  H01L29/045 ,  H01L29/1033 ,  H01L21/26586 ,  Y10S438/973

摘要： A method of increasing the performance of an FET device by aligning the channel of the FET with the �110! crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45 cc.degree. relative to each other so that, instead of the channel being aligned parallel with the �100! crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the �110! crystal direction. The mobility of the carriers is higher in the �110! crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the �110! crystal direction.

摘要翻译： 通过将FET的沟道与{100}硅晶片的[110]晶体方向对准来提高FET器件的性能的方法。 {100}硅晶片和光刻掩模的图像相对于彼此旋转45cc，使得在常规制造中，代替通道对准平行于[100]晶体方向，通道对准大致平行 与[110]晶体方向。 载流子的迁移率在[110]晶体方向上较高，从而在光刻工艺中仅仅进行微小修改来提高FET的性能。 新型FET的结果是其通道与[110]晶体方向大致平行。