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公开(公告)号:US20220066893A1
公开(公告)日:2022-03-03
申请号:US17005027
申请日:2020-08-27
Applicant: Micron Technology, Inc.
Inventor: Alan J. Wilson , Donald Martin Morgan
Abstract: Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.
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公开(公告)号:US11138107B2
公开(公告)日:2021-10-05
申请号:US16796860
申请日:2020-02-20
Applicant: Micron Technology, Inc.
Inventor: Christopher G. Wieduwilt , Alan J. Wilson
Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.
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公开(公告)号:US20210124660A1
公开(公告)日:2021-04-29
申请号:US17142828
申请日:2021-01-06
Applicant: Micron Technology, Inc.
Inventor: Alan J. Wilson
Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
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公开(公告)号:US10832791B2
公开(公告)日:2020-11-10
申请号:US16256796
申请日:2019-01-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Alan J. Wilson
IPC: G11C29/02 , G11C29/32 , G11C17/18 , G11C11/408 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C29/00 , G11C29/44
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
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公开(公告)号:US09922729B2
公开(公告)日:2018-03-20
申请号:US15703223
申请日:2017-09-13
Applicant: Micron Technology, Inc.
Inventor: Alan J. Wilson , Jeffrey Wright
IPC: G11C7/00 , G11C29/00 , G11C29/04 , G11C11/408 , G11C11/418 , G11C17/18 , G11C17/16 , G11C29/44
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
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公开(公告)号:US09793008B2
公开(公告)日:2017-10-17
申请号:US15382394
申请日:2016-12-16
Applicant: Micron Technology, Inc.
Inventor: Alan J. Wilson , Jeffrey Wright
IPC: G11C7/00 , G11C29/00 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C11/408 , G11C29/44
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
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公开(公告)号:US20160133310A1
公开(公告)日:2016-05-12
申请号:US14539331
申请日:2014-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Alan J. Wilson , Jeffrey P. Wright
IPC: G11C11/408 , G11C11/4076 , G11C16/06 , G11C11/4093
CPC classification number: G11C7/20 , G11C5/063 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093 , G11C16/06 , G11C16/20 , G11C17/18 , G11C29/021 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/14 , G11C29/46 , G11C29/70
Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
Abstract translation: 存储芯片可堆叠形成三维集成电路。 例如,硅通孔(TSV)可以允许信号垂直穿过三维集成电路。 这里公开了用于执行存储管芯的后封装修整的装置和方法,其有利地允许在存储器管芯堆叠之后对存储管芯进行修整,使得测试和修整特性相对接近将实际遇到的特性。
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