公开(公告)号：US20200212002A1

公开(公告)日：2020-07-02

申请号：US16236446

申请日：2018-12-29

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie L. Bayless

IPC: H01L23/00 ,  H01L21/66 ,  B32B37/12

Abstract: A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions configured to be individually heated independent of one another. In some embodiments, the individual regions include a first region configured to be heated to a first temperature, and a second region peripheral to the first region and configured to be heated to a second temperature different than the first temperature. In some embodiments, the bond chuck further comprises (a) a first coil disposed within the first region and configured to heat the first region to the first temperature, and (b) a second coil disposed within the second region and configured to heat the second region to the second temperature. The bond chuck can be positioned proximate a substrate of a semiconductor device such that heating the first region and/or second region affect the viscosity of an adhesive used to bond substrates of the semiconductor device to one another. Accordingly, heating the first region and/or the second region can cause the adhesive on the substrate to flow in a lateral, predetermined direction.

公开(公告)号：US10679967B2

公开(公告)日：2020-06-09

申请号：US16244939

申请日：2019-01-10

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Joseph M. Brand

IPC: H01L23/00 ,  H01L21/683

Abstract: Semiconductor device assemblies may include a carrier wafer and a thermoset adhesive on a surface of the carrier wafer. A metal barrier material may be located on the thermoset adhesive. A thermoplastic adhesive may be located on an opposite side of the metal barrier material from the thermoset adhesive. A device wafer may be located on an opposite side of the thermoplastic material from the metal barrier material. Semiconductor device processing systems may include a carrier wafer having a thermoset adhesive adhered to a surface thereof and a metal barrier material adhered to the thermoset adhesive opposite the carrier wafer. A laser apparatus may be located on an opposite side of the carrier wafer from the metal barrier material and positioned to aim a laser beam through the carrier wafer to impinge on the metal barrier material.

公开(公告)号：US10559495B2

公开(公告)日：2020-02-11

申请号：US16199788

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/304 ,  H01L21/306 ,  H01L23/28 ,  H01L21/768 ,  H01L21/02 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US20190198388A1

公开(公告)日：2019-06-27

申请号：US16199788

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/768 ,  H01L23/29 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02041 ,  H01L21/561 ,  H01L21/568 ,  H01L23/298 ,  H01L23/3128

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US10326044B2

公开(公告)日：2019-06-18

申请号：US15680461

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless

IPC: H01L21/00 ,  H01L29/40 ,  H01L33/00 ,  H01L21/78 ,  H01L23/538

Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

公开(公告)号：US20190148335A1

公开(公告)日：2019-05-16

申请号：US16244939

申请日：2019-01-10

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Joseph M. Brand

IPC: H01L23/00 ,  H01L21/683

Abstract: Semiconductor device assemblies may include a carrier wafer and a thermoset adhesive on a surface of the carrier wafer. A metal barrier material may be located on the thermoset adhesive. A thermoplastic adhesive may be located on an opposite side of the metal barrier material from the thermoset adhesive. A device wafer may be located on an opposite side of the thermoplastic material from the metal barrier material. Semiconductor device processing systems may include a carrier wafer having a thermoset adhesive adhered to a surface thereof and a metal barrier material adhered to the thermoset adhesive opposite the carrier wafer. A laser apparatus may be located on an opposite side of the carrier wafer from the metal barrier material and positioned to aim a laser beam through the carrier wafer to impinge on the metal barrier material

公开(公告)号：US09716023B2

公开(公告)日：2017-07-25

申请号：US14332096

申请日：2014-07-15

Applicant: Micron Technology, Inc.

Inventor： Sharon N. Farrens ,  Neal Bowen ,  Andrew M. Bayless

IPC: B29C53/82 ,  B29C65/00 ,  B32B37/00 ,  B32B7/14 ,  C09J5/04 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/683 ,  B32B37/12 ,  B32B5/14 ,  B32B7/12 ,  B32B38/00

CPC classification number: H01L21/6835 ,  B32B5/142 ,  B32B7/12 ,  B32B37/1292 ,  B32B38/105 ,  B32B2250/02 ,  B32B2255/00 ,  B32B2405/00 ,  B32B2457/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A method of bonding a device wafer to a carrier wafer includes disposing a first adhesive over a central portion of a carrier wafer, the first adhesive having a first glass transition temperature, disposing a second adhesive over a peripheral portion of the carrier wafer, the second adhesive having a second glass transition temperature greater than the first glass transition temperature, and bonding the first adhesive to an active front side of the device wafer and the second adhesive to a peripheral portion of the front side of the device wafer. Related assemblies may be used in such methods.

公开(公告)号：US20250046731A1

公开(公告)日：2025-02-06

申请号：US18781862

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie L. Bayless

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/67 ,  H01L21/78

Abstract: Methods, apparatuses, and systems related to a semiconductor structure having a thinning-based alignment mark. The alignment mark may be formed by causing structural an alteration within a thickness of an initial semiconductor wafer and then thinning the initial semiconductor wafer. The thinning process may lead to a different removal rate of the altered portion and a corresponding mark at the end of the thinning process. The resulting mark may be used to identify a relative location of circuits on the thinned wafer for subsequent processing or bonding.

公开(公告)号：US12100661B2

公开(公告)日：2024-09-24

申请号：US18368987

申请日：2023-09-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/53238 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US12087697B2

公开(公告)日：2024-09-10

申请号：US18214378

申请日：2023-06-26

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L25/0657

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.