-
51.发明授权公开(公告)号：US11781918B2
公开(公告)日：2023-10-10
申请号：US16509262
申请日：2019-07-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan
Abstract: A temperature sensor is disclosed. The temperature sensor includes an analog core having at least first and second circuit nodes and configured to provide a temperature dependent output, a multiplexer coupled to the first and second circuit nodes and configured for at least first and second states in each of which the first circuit node couples to a different circuit element and in each of which the second circuit node couples to a different circuit element, and a controller coupled to the analog core and configured to provide a temperature measurement that is an average of at least first and second readings of the temperature dependent output of the analog core, the first reading taken while the multiplexer is in the first state, and the second reading taken while the multiplexer is in the second state.
-
公开(公告)号：US20230206980A1
公开(公告)日：2023-06-29
申请号：US17565119
申请日：2021-12-29
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4097
CPC classification number: G11C11/40611 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4097 , G11C11/4099
Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.
-
公开(公告)号：US11450373B2
公开(公告)日：2022-09-20
申请号：US17003163
申请日：2020-08-26
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C5/14 , G11C11/4074 , G11C11/4091 , H03H7/06 , G11C7/14 , G05F1/575 , G11C11/4063
Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.
-
公开(公告)号：US20220200538A1
公开(公告)日：2022-06-23
申请号：US17127172
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Zhi Qi Huang , Dong Pan
Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.
-
公开(公告)号：US11315627B1
公开(公告)日：2022-04-26
申请号：US16950593
申请日：2020-11-17
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4091 , G11C11/4094 , G11C11/4063 , G11C11/22 , G11C11/408
Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.
-
Patent Agency Ranking
公开(公告)号：US11302386B2
公开(公告)日：2022-04-12
申请号：US17133755
申请日：2020-12-24
Applicant: Micron Technology, Inc.
IPC: G11C11/4093 , G11C11/4074
Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
-
公开(公告)号：US20220059158A1
公开(公告)日：2022-02-24
申请号：US16997659
申请日：2020-08-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4096
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
-
公开(公告)号：US20210359598A1
公开(公告)日：2021-11-18
申请号：US16321769
申请日：2018-12-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
-
公开(公告)号：US20210336612A1
公开(公告)日：2021-10-28
申请号：US16472773
申请日：2018-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhiqi Huang , Weilu Chu , Dong Pan
IPC: H03K5/134 , G11C11/4076 , G11C11/4093
Abstract: Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.
-
公开(公告)号：US10892005B1
公开(公告)日：2021-01-12
申请号：US16696225
申请日：2019-11-26
Applicant: Micron Technology, Inc.
IPC: G11C11/4093 , G11C11/4074
Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
-
-
-
-
-
-
-
-
-
Search Results
125
records
(took 0.026 seconds)
