公开(公告)号：US09940981B2

公开(公告)日：2018-04-10

申请号：US15688348

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G06F12/02 ,  G06F9/302 ,  G06F9/30

CPC classification number: G11C7/10 ,  G06F7/00 ,  G06F7/535 ,  G06F9/3001 ,  G06F12/02 ,  G06F12/0207 ,  G11C7/1006

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

公开(公告)号：US20180082756A1

公开(公告)日：2018-03-22

申请号：US15822748

申请日：2017-11-27

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C29/12 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G11C29/14 ,  G11C29/32 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/10 ,  G11C7/10

CPC classification number: G11C29/1201 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/785 ,  G11C7/065 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/10 ,  G11C29/14 ,  G11C29/32 ,  Y02D10/13

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US09904515B2

公开(公告)日：2018-02-27

申请号：US14834065

申请日：2015-08-24

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G06F7/53 ,  H03K19/177 ,  G11C7/10 ,  G11C11/4091

CPC classification number: G06F7/523 ,  G06F7/53 ,  G06G7/16 ,  G11C7/1006 ,  G11C11/4091 ,  H03K19/17732

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US09898252B2

公开(公告)日：2018-02-20

申请号：US14833680

申请日：2015-08-24

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G06F7/523 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

公开(公告)号：US20170358333A1

公开(公告)日：2017-12-14

申请号：US15688348

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G06F9/30 ,  G06F12/02

CPC classification number: G11C7/10 ,  G06F7/00 ,  G06F7/535 ,  G06F9/3001 ,  G06F12/02 ,  G06F12/0207 ,  G11C7/1006

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

公开(公告)号：US09697876B1

公开(公告)日：2017-07-04

申请号：US15057736

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C11/4091 ,  G11C19/28

Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.

公开(公告)号：US20170133066A1

公开(公告)日：2017-05-11

申请号：US15410199

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C8/10

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

公开(公告)号：US20160266899A1

公开(公告)日：2016-09-15

申请号：US15065483

申请日：2016-03-09

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F9/30 ,  G06F15/78

CPC classification number: G06F9/3004 ,  G06F7/607 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F15/7821 ,  G06F15/7839 ,  Y02D10/12 ,  Y02D10/13

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Abstract translation: 本公开的示例提供了用于确定存储器中的向量群体计数的装置和方法。 示例性方法包括：使用感测电路确定存储在存储器阵列中的矢量的固定长度元素的数量的向量群体计数。

公开(公告)号：US20160063284A1

公开(公告)日：2016-03-03

申请号：US14834065

申请日：2015-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sanjay Tiwari

IPC: G06G7/16 ,  G06F7/523

CPC classification number: G06F7/523 ,  G06F7/53 ,  G06G7/16 ,  G11C7/1006 ,  G11C11/4091 ,  H03K19/17732

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行多可变位长度乘法运算的装置和方法。 示例性方法包括对第一向量和第二向量执行乘法运算。 第一矢量包括存储在耦合到存储器阵列的第一存取线和多条感测线的一组存储器单元中的多个第一元件。 第二向量包括存储在耦合到第二访问线的一组存储器单元中的多个第二元素和存储器阵列的感测线的数量。 示例性乘法运算可以包括执行多个AND运算，或运算和SHIFT运算，而不经由输入/输出（I / O）线传送数据。

公开(公告)号：US20160062733A1

公开(公告)日：2016-03-03

申请号：US14833680

申请日：2015-08-24

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523

CPC classification number: G06F7/523 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行乘法运算的装置和方法。 一个示例性方法包括对存储在耦合到存储器阵列的一组存储器单元和多个存储器阵列的感测线的存储器单元中的第一元件和存储在耦合到第二存储器单元的存储器单元组中的第二元件执行乘法运算 访问线和存储器阵列的感测线的数量。 该方法可以包括在不经由输入/输出（I / O）线路传送数据的情况下执行的数字操作。