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    Phase change memory stack with treated sidewalls
    51.
    发明授权
    Phase change memory stack with treated sidewalls 有权
    具有处理侧壁的相变存储器堆叠

    公开(公告)号：US09306159B2

    公开(公告)日：2016-04-05

    申请号：US14266415

    申请日：2014-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

    Abstract translation: 已经公开了用于制造存储器件的存储器件和方法。 一种这样的方法包括从多个元件形成存储器堆叠。 在存储器堆叠的至少一个侧壁上形成粘附物质，其中粘附物质具有梯度结构，其导致粘附物质与存储器堆叠的元件混合以终止元件的不满足的原子键。 梯度结构还包括在至少一个侧壁的外表面上的粘附物质的膜。 将电介质材料注入到粘附物质的膜中以形成侧壁衬里。

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    52.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 有权
    相位变化的存储堆栈与处理的SIDEWALLS

    公开(公告)号：US20150318467A1

    公开(公告)日：2015-11-05

    申请号：US14266365

    申请日：2014-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Swapnil Lengade ,  Everett Allen McTeer ,  Shu Qin

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.

    Abstract translation: 已经公开了用于制造存储器件的存储器件和方法。 一种这样的存储器件包括形成在字线材料上的第一电极材料。 在第一电极材料上形成选择器装置材料。 第二电极材料形成在选择器装置材料上。 在第二电极材料上形成相变材料。 在相变材料上形成第三电极材料。 粘附物质是等离子体掺杂到存储器堆叠的侧壁中，并且衬垫材料形成在存储器堆叠的侧壁上。 粘附物质与存储器堆叠和侧壁衬套的元件混合以终止元件和侧壁衬套的不满足的原子键。

    DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING
    53.
    发明申请
    DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING 审中-公开
    静电强化半导体结合装置，系统及方法

    公开(公告)号：US20150221540A1

    公开(公告)日：2015-08-06

    申请号：US14173489

    申请日：2014-02-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shu Qin ,  Ming Zhang

    IPC: H01L21/683 ,  H01L21/762

    CPC classification number: H01L21/6833 ,  H01L21/76251

    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

    Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，一种用于增强晶片接合的方法包括将基板组件定位在与电极直接接触的单极静电卡盘上，将导体电耦合到位于第一基板顶部的第二基板，以及向电极施加电压 从而在第一基板和第二基板之间产生在第一和第二基板之间产生静电力的电位差。

    Memory Cells and Methods of Forming Memory Cells
    54.
    发明申请
    Memory Cells and Methods of Forming Memory Cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20150179936A1

    公开(公告)日：2015-06-25

    申请号：US14618936

    申请日：2015-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Martin Schubert ,  Shu Qin ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

    Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.

    Abstract translation: 一些实施例包括具有第一电极的存储器单元，以及在第一电极之上并直接抵靠第一电极的中间材料。 中间材料包括对应于碳和硼之一或两者的稳定物质。 存储单元还具有超过并直接抵靠中间材料的开关材料，开关材料上方的离子储存器材料以及离子储存器材料上的第二电极。 一些实施例包括形成存储器单元的方法。

    SYSTEMS AND METHODS FOR PLASMA PROCESSING OF MICROFEATURE WORKPIECES
    57.
    发明申请
    SYSTEMS AND METHODS FOR PLASMA PROCESSING OF MICROFEATURE WORKPIECES 有权
    用于等离子体加工微孔工件的系统和方法

    公开(公告)号：US20140197134A1

    公开(公告)日：2014-07-17

    申请号：US14218428

    申请日：2014-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Allen McTeer

    IPC: H01J37/32 ,  C23C16/52 ,  C23C14/54

    CPC classification number: H01J37/32917 ,  C23C14/54 ,  C23C16/52 ,  G01N21/73 ,  H01J37/32935 ,  H01J37/32972

    Abstract: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

    Abstract translation: 本文公开了微型工件的等离子体处理的系统和方法。 在一个实施例中，一种方法包括在微型工件位于腔室中的同时在腔室中产生等离子体，测量等离子体的光发射，以及基于所测量的光发射来确定等离子体的参数。 该参数可以是等离子体的离子密度或其他参数。

    SYSTEMS AND METHODS FOR PLASMA DOPING MICROFEATURE WORKPIECES
    58.
    发明申请
    SYSTEMS AND METHODS FOR PLASMA DOPING MICROFEATURE WORKPIECES 有权
    用于等离子体显微镜工作的系统和方法

    公开(公告)号：US20140144379A1

    公开(公告)日：2014-05-29

    申请号：US14171430

    申请日：2014-02-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shu Qin ,  Allen McTeer

    IPC: C23C14/48

    CPC classification number: C23C14/48 ,  C23C14/16 ,  C23C16/28 ,  C23C16/515 ,  C23C16/517 ,  H01J37/32412 ,  H01L21/2236 ,  Y10S438/914

    Abstract: Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a workpiece includes generating a plasma in a chamber, selectively applying a pulsed electrical potential to the workpiece with a duty cycle of between approximately 20 percent and approximately 50 percent, and implanting an ion specie into the region of the workpiece.

    Abstract translation: 本文公开了等离子体掺杂微型工件的系统和方法。 在一个实施例中，将硼离子注入到工件的区域中的方法包括在腔室中产生等离子体，以大约20％至大约50％的占空比选择性地将脉冲电势施加到工件，并且植入 离子种类进入工件的区域。

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