公开(公告)号：US20180061477A1

公开(公告)日：2018-03-01

申请号：US15679042

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C8/16 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  H01L27/108

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/06 ,  G11C7/062 ,  G11C7/18 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/108 ,  H01L27/10897

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20180061468A1

公开(公告)日：2018-03-01

申请号：US15678978

申请日：2017-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11502

CPC classification number: G11C11/221 ,  G11C11/2253 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11514 ,  H01L28/55 ,  H01L28/90

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US09318187B2

公开(公告)日：2016-04-19

申请号：US13948951

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/08

Abstract: A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data line for charge sharing. The activation device can then be disabled to isolate the memory cell capacitor from the active data line. The state of the memory cell can then be sensed while the memory cell capacitor is isolated from the active data line. After the sense operation, the activation device can be re-enabled in order to restore the data to the memory cell capacitor that was destroyed during the sense operation.

Abstract translation: 描述了一种在存储单元电容器与数据线隔离的同时感测存储单元的状态的方法和存储器。 可以使存储器单元的激活装置能够将存储单元电容器耦合到有源数据线的寄生电容用于电荷共享。 然后可以禁用激活装置以将存储单元电容器与活动数据线隔离。 然后可以在存储单元电容器与有源数据线隔离的同时感测存储单元的状态。 在感测操作之后，可以重新启用激活装置，以便将数据恢复到在感测操作期间被破坏的存储单元电容器。

公开(公告)号：US12114474B2

公开(公告)日：2024-10-08

申请号：US17877628

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/24 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827 ,  H10B12/50

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20220367465A1

公开(公告)日：2022-11-17

申请号：US17877628

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20220028447A1

公开(公告)日：2022-01-27

申请号：US17497382

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/12 ,  G11C7/06 ,  G11C8/08

Abstract: An example apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.

公开(公告)号：US20210398582A1

公开(公告)日：2021-12-23

申请号：US17370515

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20210271377A1

公开(公告)日：2021-09-02

申请号：US17325896

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Patrick Mullarkey

IPC: G06F3/0484 ,  G06F3/00 ,  G06F16/29 ,  G06F16/70 ,  G06F16/54 ,  G06F16/904 ,  G06F16/74

Abstract: Computer-readable media and methods for a geospatial image map are disclosed. A computer-readable medium has computer-readable instructions stored thereon. The computer-readable instructions are configured to instruct one or more processors to display a map of a selected geographic region on an electronic display. The map includes geographic sub-regions displayed within the map. The computer-readable instructions are configured to instruct the one or more processors to select discrete images corresponding to the geographic sub-regions, and display the discrete images at the same time on the electronic display as an overlay to the map. A method includes displaying a map of a selected geographic region, displaying geographic sub-regions of the selected geographic region, selecting discrete images corresponding to the geographic sub-regions and one or more selected categories, and displaying the discrete images simultaneously on the electronic display as an overlay to the map.

公开(公告)号：US20210183428A1

公开(公告)日：2021-06-17

申请号：US17171853

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US10943642B2

公开(公告)日：2021-03-09

申请号：US16838618

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/4094

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.