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公开(公告)号：US09661252B2
公开(公告)日：2017-05-23
申请号：US15059959
申请日：2016-03-03
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: An image capturing device includes: an image capturing section having a plurality of pixels disposed in a matrix and configured to output a pixel signal via a first signal line connected to pixels arranged in a first direction among the plurality of pixels; a plurality of calculators including: a comparator configured to compare a magnitude of a first analog signal with a threshold value to generate a digital value according to a comparison result; an amplification section configured to amplify the first analog signal by multiplying the first analog signal by an amplification degree β (1
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公开(公告)号：US09621776B2
公开(公告)日：2017-04-11
申请号：US14847226
申请日：2015-09-08
Applicant: OLYMPUS CORPORATION
Inventor： Makoto Ono , Nana Akahane , Masashi Saito , Yoshio Hagihara , Susumu Yamazaki
CPC classification number: H04N5/2256 , A61B1/00018 , A61B1/045 , H04N5/23241 , H04N2005/2255
Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.
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公开(公告)号：US09609258B2
公开(公告)日：2017-03-28
申请号：US14883013
申请日：2015-10-14
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: An A/D conversion circuit includes: a reference signal generation section that includes an integrator circuit having a first constant current source and generates a reference signal that changes in accordance with a constant current output by the first constant current source; a comparison section that executes a comparison process between an analog signal and the reference signal and terminates the comparison process; a clock generation section that includes a delay section having delay units for delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source, and outputs a lower phase signal based on the signals output from the delay units; a latch section that latches the lower phase signal at a timing related to the termination of the comparison process; and a count section that counts a clock based on the lower phase signal.
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公开(公告)号：US20160044261A1
公开(公告)日：2016-02-11
申请号：US14883013
申请日：2015-10-14
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: An A/D conversion circuit includes: a reference signal generation section that includes an integrator circuit having a first constant current source and generates a reference signal that changes in accordance with a constant current output by the first constant current source; a comparison section that executes a comparison process between an analog signal and the reference signal and terminates the comparison process; a clock generation section that includes a delay section having delay units for delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source, and outputs a lower phase signal based on the signals output from the delay units; a latch section that latches the lower phase signal at a timing related to the termination of the comparison process; and a count section that counts a clock based on the lower phase signal.
Abstract translation: A / D转换电路包括：参考信号产生部分，包括具有第一恒流源的积分器电路，并产生根据由第一恒流源输出的恒定电流而变化的参考信号; 比较部，执行模拟信号与参考信号之间的比较处理，并结束比较处理; 时钟生成部，其具有延迟部，该延迟部具有用于将输入信号延迟预定时间的延迟部，并且根据由第二恒定电流源输出的恒定电流输出延迟的输入信号，并且根据所述信号输出下部相位信号 延时单元输出; 锁存部，其以与比较处理结束相关的定时锁存下相位信号; 以及基于下相位信号对时钟进行计数的计数部。
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公开(公告)号：US09204076B2
公开(公告)日：2015-12-01
申请号：US14607786
申请日：2015-01-28
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
CPC classification number: H04N5/378 , H03M1/14 , H03M1/56 , H04N5/357 , H04N5/3765
Abstract: An imaging apparatus includes a clock generation unit that generates a plurality of phase signals having phases different from one another, a signal transmission unit provided to correspond to the plurality of phase signals and having a plurality of signal transmission circuits, and a latch unit having a plurality of latch circuits that latches the phase signals transmitted by the signal transmission unit at a timing of an end of a comparison process performed by a comparison unit. A configuration of the signal transmission circuit that transmits a first phase signal is substantially the same as a configuration of the signal transmission circuit that transmits a second phase signal different from the first phase signal. A configuration of the latch circuit that latches the first phase signal is substantially the same as a configuration of the latch circuit that latches the second phase signal.
Abstract translation: 一种成像装置，包括：时钟生成单元，其生成具有彼此不同的相位的多个相位信号;信号发送单元，被提供为对应于所述多个相位信号，并具有多个信号发送电路;以及锁存单元，具有： 多个锁存电路，在比较单元执行的比较处理结束的定时锁存由信号发送单元发送的相位信号。 发送第一相位信号的信号发送电路的结构与发送与第一相位信号不同的第二相位信号的信号发送电路的结构基本相同。 锁存第一相位信号的锁存电路的配置与锁存第二相位信号的锁存电路的配置基本相同。
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Patent Agency Ranking
公开(公告)号：US20150326800A1
公开(公告)日：2015-11-12
申请号：US14699242
申请日：2015-04-29
Applicant: OLYMPUS CORPORATION
Inventor： Susumu Yamazaki , Yoshio Hagihara
CPC classification number: H04N5/217 , H04N5/2173 , H04N5/225 , H04N5/2253 , H04N5/2256 , H04N5/335 , H04N5/357 , H04N5/3575 , H04N5/3698 , H04N5/37452 , H04N5/37457 , H04N2005/2255
Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion sections configured to generate a signal charge according to an amount of an incident light and disposed in a matrix, a first accumulation section configured to accumulate the signal charge, a first transfer section configured to transfer the signal charge from the photoelectric conversion sections to the first accumulation section, a second accumulation section configured to accumulate the signal charge accumulated in the first accumulation section, a second transfer section configured to transfer the signal charge accumulated in the first accumulation section to the second accumulation section, a reset section configured to reset the signal charge accumulated in the second accumulation section, an output section configured to output a signal according to the signal charge accumulated in the second accumulation section, and first and second control sections configured to control each section for every row or column.
Abstract translation: 一种固体摄像装置，包括：多个光电转换部，被配置为根据入射光的量生成信号电荷并配置成矩阵状;第一累积部，被配置为累积信号电荷;第一转印部，被配置为 将信号电荷从光电转换部分传送到第一累积部分，第二累积部分，被配置为累积在第一累积部分中累积的信号电荷;第二传送部分，被配置为将累积在第一累积部分中的信号电荷传送到 第二累积部分，复位部分，被配置为复位在第二累积部分中累积的信号电荷;输出部分，被配置为根据累积在第二累积部分中的信号电荷输出信号;以及第一和第二控制部分， 部分为每一行 或列。
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公开(公告)号：US09106860B2
公开(公告)日：2015-08-11
申请号：US13952947
申请日：2013-07-29
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N5/378
CPC classification number: H04N5/378
Abstract: An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.
Abstract translation: AD转换电路可以包括：参考信号生成单元; 比较单位 时钟发生单元; 闩锁单元; 计数单位 以及包括检测电路和编码电路的编码单元，所述检测电路执行检测锁存单元中锁存的多个下相位信号的信号组中n个下相位信号的逻辑状态的第一检测操作， 当从时钟发生单元输出的多个下相位信号被布置为信号组时，当检测到n个较低相位信号的逻辑状态被检测为检测电路输出状态检测信号时，与信号组相同的顺序 在第一检测操作中的预定逻辑状态，编码电路根据从检测电路输出的状态检测信号进行编码。
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公开(公告)号：US20140077065A1
公开(公告)日：2014-03-20
申请号：US14027653
申请日：2013-09-16
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
CPC classification number: H03M1/34 , H03M1/0624 , H03M1/56 , H04N5/374 , H04N5/378
Abstract: An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.
Abstract translation: AD转换电路和固态成像装置在确保计数时钟的选择的自由度的同时减少编码较低相位信号的误差的发生。 检测电路执行检测由锁存单元锁存的多个下相信号被布置的信号组中的m（m是2或更多的自然数）的相位信号的逻辑状态的操作，同时选择m较低 以使其顺序与信号组的顺序相同，并在检测到m个下相位信号的逻辑状态处于预定的逻辑状态时输出状态检测信号 检测操作。 预定顺序根据预定信号和编码方法来定义。
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公开(公告)号：US20130234004A1
公开(公告)日：2013-09-12
申请号：US13785986
申请日：2013-03-05
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N5/378
CPC classification number: H04N5/378 , H01L27/14 , H04N5/3575
Abstract: In an imaging device, one end of a capacitive element is connected to a second input terminal to which a reference signal Ramp is applied, and the other end of the capacitive element is connected to a voltage source during a reset operation and to a voltage source after the reset operation through a switching element. As a result, the voltage of the second input terminal is changed such that a voltage difference between the first input terminal and the second input terminal becomes a voltage guaranteeing a comparison operation after the reset operation.
Abstract translation: 在成像装置中，电容元件的一端连接到施加了参考信号Ramp的第二输入端子，并且电容元件的另一端在复位操作期间连接到电压源，并连接到电压源 在通过开关元件的复位操作之后。 结果，改变第二输入端子的电压，使得第一输入端子和第二输入端子之间的电压差成为保证复位操作之后的比较操作的电压。
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公开(公告)号：US20130182090A1
公开(公告)日：2013-07-18
申请号：US13742920
申请日：2013-01-16
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N5/335
CPC classification number: H04N5/335 , H04N5/37213 , H04N5/3741
Abstract: An image pickup device includes, but is not limited to: an image pickup unit; a first selector; and an output unit. The image pickup unit includes a plurality of pixels arranged in a matrix. Each of the pixels is configured to generate, store, and output a pixel signal. The first selector is configured to select a column of the matrix and control the pixels arranged in the column selected. The output unit is configured to convert into a voltage signal, the pixel signal output from each of the pixels.
Abstract translation: 图像拾取装置包括但不限于：图像拾取单元; 第一选择器 和输出单元。 图像拾取单元包括以矩阵排列的多个像素。 每个像素被配置为生成，存储和输出像素信号。 第一选择器被配置为选择矩阵的列并且控制排列在所选列中的像素。 输出单元被配置为将每个像素输出的像素信号转换为电压信号。
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