公开(公告)号：US11096566B2

公开(公告)日：2021-08-24

申请号：US15921937

申请日：2018-03-15

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： A61B1/05 ,  H04N5/378 ,  A61B1/00 ,  A61B1/045 ,  G02B23/24 ,  H04N5/235 ,  H04N5/225

摘要： An endoscope system includes an imaging element, a voltage-current conversion circuit, a first coaxial cable, and an impedance conversion circuit. The imaging element generates a first voltage. The voltage-current conversion circuit is disposed inside or outside the imaging element and converts the first voltage into a first current. The first coaxial cable has a first conductor and a second conductor. The second conductor is disposed outside the first conductor. The first current is transmitted through the first conductor. The first current transmitted through the first conductor is input to the impedance conversion circuit. The impedance conversion circuit outputs a second current according to the first current. A second voltage according to the first current is input to the second conductor.

公开(公告)号：US10154218B2

公开(公告)日：2018-12-11

申请号：US15455270

申请日：2017-03-10

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/376 ,  H03M1/56 ,  H04N5/378 ,  H03K5/15 ,  H03M1/20 ,  H03M7/30 ,  H04N5/374 ,  H04N5/3745 ,  H03M1/12 ,  H03M1/50

摘要： An encoding circuit includes a clock generating unit having a delay circuit in which n (n is a power of 2) delay units are connected together a latch unit configured to latch the plurality of delayed signals; and an encoding unit configured to encode state of each of the plurality of delayed signals, wherein the encoding unit encodes the state of each of the plurality of delayed signals by performing: a first operation of determining a position at which logic states of two or more delayed signals in a signal group change from High to Low, a second operation of determining a position at which logic states of two or more delayed signals in the signal group change from Low to High, and a third operation of determining that logic states of two or more signals including at least one delayed signal in the signal group are predetermined states.

公开(公告)号：US20180153374A1

公开(公告)日：2018-06-07

申请号：US15886262

申请日：2018-02-01

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： A61B1/00

CPC分类号： A61B1/00011 ,  A61B1/00006 ,  A61B1/00009 ,  A61B1/00018 ,  A61B1/00045 ,  A61B1/045 ,  H03F1/56 ,  H03F3/45475 ,  H03F3/505

摘要： A signal transmission circuit includes an impedance conversion circuit and a current-voltage conversion circuit. A first current is input to the impedance conversion circuit. The impedance conversion circuit outputs a second current according to the first current. The current-voltage conversion circuit converts the second current output from the impedance conversion circuit into a voltage. The impedance conversion circuit includes a first current source and a current output circuit. The first current source generates a reference current. The current output circuit outputs the second current according to the difference between the first current and the reference current or the sum of the first current and the reference current.

公开(公告)号：US20170163922A1

公开(公告)日：2017-06-08

申请号：US15435614

申请日：2017-02-17

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/3745 ,  H01L27/146

CPC分类号： H04N5/3745 ,  H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/378

摘要： A first voltage line supplies a constant first voltage in column circuits of an imaging device. A second voltage line supplies a second voltage that is lower than the first voltage and is constant. A third voltage line supplies a constant third voltage. A fourth voltage line supplies a fourth voltage that is lower than the third voltage and is constant. The first voltage line is electrically connected to a drain of an NMOS transistor, and the third voltage line is electrically connected to a gate of the NMOS transistor. The second voltage line is electrically connected to a drain of a PMOS transistor, and the fourth voltage line is electrically connected to a gate of the PMOS transistor.

公开(公告)号：US20160088244A1

公开(公告)日：2016-03-24

申请号：US14960899

申请日：2015-12-07

申请人： OLYMPUS CORPORATION

发明人： Susumu Yamazaki ,  Yoshio Hagihara

IPC分类号： H04N5/369 ,  H03K17/16 ,  G11C27/02 ,  H01L27/146

CPC分类号： H04N5/369 ,  G11C27/02 ,  G11C27/024 ,  H01L23/5223 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/14636 ,  H03K17/161 ,  H04N5/378

摘要： A switching circuit comprising: a semiconductor layer including a source region, a drain region, and a channel region; a gate electrode disposed to be opposite to the channel region; a source wiring formed of a first material having higher conductivity than the semiconductor layer; a drain wiring formed of a second material having higher conductivity than the semiconductor layer; and a decoupling wiring formed of a third material having higher conductivity than the semiconductor layer, wherein the source region and the drain region are in a conductive state in a first period according to a voltage of the gate electrode, and the source region and the drain region are in a non-conductive state in a second period different from the first period, and wherein a voltage of the decoupling wiring is constant in at least a partial period of the second period.

摘要翻译： 一种开关电路，包括：包括源极区，漏极区和沟道区的半导体层; 设置成与沟道区相对的栅电极; 由与半导体层相比导电率高的第一材料形成的源极布线; 由与半导体层相比导电性高的第二材料形成的漏极布线; 以及由比所述半导体层高的导电性的第三材料形成的去耦布线，其中所述源极区域和所述漏极区域在第一周期中根据所述栅电极的电压处于导通状态，并且所述源极区域和所述漏极 区域在与第一周期不同的第二周期中处于非导通状态，并且其中去耦布线的电压在第二周期的至少部分周期中是恒定的。

公开(公告)号：US09106253B2

公开(公告)日：2015-08-11

申请号：US14027653

申请日：2013-09-16

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H03M1/34 ,  H04N5/378 ,  H03M1/06 ,  H04N5/374 ,  H03M1/56

CPC分类号： H03M1/34 ,  H03M1/0624 ,  H03M1/56 ,  H04N5/374 ,  H04N5/378

摘要： An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.

摘要翻译： AD转换电路和固态成像装置在确保计数时钟的选择的自由度的同时减少编码较低相位信号的误差的发生。 检测电路执行检测由锁存单元锁存的多个下相信号被布置的信号组中的m（m是2或更多的自然数）的相位信号的逻辑状态的操作，同时选择m较低 以使其顺序与信号组的顺序相同，并在检测到m个下相位信号的逻辑状态处于预定的逻辑状态时输出状态检测信号 检测操作。 预定顺序根据预定信号和编码方法来定义。

公开(公告)号：US20150144771A1

公开(公告)日：2015-05-28

申请号：US14607786

申请日：2015-01-28

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/378

CPC分类号： H04N5/378 ,  H03M1/14 ,  H03M1/56 ,  H04N5/357 ,  H04N5/3765

摘要： An imaging apparatus includes a clock generation unit that generates a plurality of phase signals having phases different from one another, a signal transmission unit provided to correspond to the plurality of phase signals and having a plurality of signal transmission circuits, and a latch unit having a plurality of latch circuits that latches the phase signals transmitted by the signal transmission unit at a timing of an end of a comparison process performed by a comparison unit. A configuration of the signal transmission circuit that transmits a first phase signal is substantially the same as a configuration of the signal transmission circuit that transmits a second phase signal different from the first phase signal. A configuration of the latch circuit that latches the first phase signal is substantially the same as a configuration of the latch circuit that latches the second phase signal.

摘要翻译： 一种成像装置，包括：时钟生成单元，其生成具有彼此不同的相位的多个相位信号;信号发送单元，被提供为对应于所述多个相位信号，并具有多个信号发送电路;以及锁存单元，具有： 多个锁存电路，在比较单元执行的比较处理结束的定时锁存由信号发送单元发送的相位信号。 发送第一相位信号的信号发送电路的结构与发送与第一相位信号不同的第二相位信号的信号发送电路的结构基本相同。 锁存第一相位信号的锁存电路的配置与锁存第二相位信号的锁存电路的配置基本相同。

公开(公告)号：US08994575B2

公开(公告)日：2015-03-31

申请号：US13759383

申请日：2013-02-05

申请人： Olympus Corporation

发明人： Yoshio Hagihara

IPC分类号： H03M1/56 ,  H03K21/00 ,  G04F10/00 ,  H04N5/374 ,  H04N5/378 ,  H01L27/146 ,  H03M1/34

CPC分类号： H03K21/00 ,  G04F10/005 ,  H01L27/14601 ,  H03M1/34 ,  H03M1/56 ,  H04N5/3742 ,  H04N5/378

摘要： A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.

摘要翻译： 时间检测电路可以包括：延迟单元，被配置为具有多个延迟单元，每个延迟单元延迟并输出输入信号，并且在与第一脉冲的输入有关的第一定时开始操作; 锁存单元，被配置为锁存所述多个延迟单元的逻辑状态; 计数单元，被配置为基于从所述多个延迟单元中的一个延迟单元输出的时钟来执行计数操作; 计数锁存单元，被配置为锁存所述计数单元的状态; 以及闩锁控制单元，被配置为在与第二脉冲的输入相关的第二定时使能所述锁存单元，并且使所述锁存单元和所述计数锁存单元在从所述锁存单元和所述计数锁存单元经过预定时间的第三定时执行锁存器 第二时间。

公开(公告)号：US20140036125A1

公开(公告)日：2014-02-06

申请号：US13953272

申请日：2013-07-29

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/3745

CPC分类号： H04N5/37455 ,  H04N5/378

摘要： An imaging apparatus capable of reducing deterioration of AD conversion accuracy is provided, wherein, when performing the AD conversion on a pixel signal corresponding to a reset level, a latch control unit causes a latch circuit of a latch unit to enter an enabled state (third timing) at a first timing according to a comparison start in a comparing unit, and then causes the latch circuit of the latch unit to execute latching at a fourth timing at which a predetermined time has lapsed from a second timing according to a comparison end in the comparing unit. Further, when performing the AD conversion on the pixel signal corresponding to the signal level, the latch control unit causes the latch circuit of the latch unit to enter the enabled state at the second timing according to the comparison end in the comparing unit.

摘要翻译： 提供一种能够降低AD转换精度降低的成像装置，其中，当对与复位电平相对应的像素信号执行AD转换时，锁存器控制单元使闩锁单元的锁存电路进入使能状态（第三 定时）根据比较单元中的比较开始在第一定时，然后使得锁存单元的锁存电路在第二定时从根据比较结束的第二定时经过预定时间的第四定时执行锁存 比较单位。 此外，当对与信号电平相对应的像素信号执行AD转换时，锁存器控制单元根据比较单元中的比较结束，使闩锁单元的锁存电路在第二定时进入使能状态。

公开(公告)号：US20200221045A1

公开(公告)日：2020-07-09

申请号：US16823968

申请日：2020-03-19

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/3745 ,  A61B1/04 ,  A61B1/05 ,  H04N5/378 ,  H04N5/369

摘要： An imaging device includes a first substrate and a second substrate stacked on the first substrate. The first substrate includes a plurality of pixels. Each pixel block includes all of the pixels disposed in one or more columns in an array of the plurality of pixels. The second substrate includes a plurality of AD conversion circuits configured to convert a pixel signal read from two or more pixels belonging to the pixel block corresponding to the AD conversion circuit to a digital signal. For all combinations of two pixel blocks adjacent to each other in the first substrate, two AD conversion circuits corresponding to the adjacent two pixel blocks are adjacent to each other in the second substrate.